Commit 54877957 authored by Scott Wood's avatar Scott Wood
Browse files

powerpc/fsl: Use new clockgen binding 



The driver retains compatibility with old device trees, but we don't
want the old nodes lying around to be copied, or used as a reference
(some of the mux options are incorrect), or even just being clutter.

Signed-off-by: default avatarScott Wood <oss@buserror.net>
Signed-off-by: default avatarTang Yuantian <andy.tang@nxp.com>
[scottwood: removed sysclk node added by Andy]
Signed-off-by: default avatarScott Wood <oss@buserror.net>
parent 0deae39c

arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -70,14 +70,14 @@ 
		cpu0: PowerPC,e6500@0 {

			device_type = "cpu";

			reg = <0 1>;

			clocks = <&mux0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			reg = <2 3>;

			clocks = <&mux0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -75,28 +75,28 @@ 
		cpu0: PowerPC,e6500@0 {

			device_type = "cpu";

			reg = <0 1>;

			clocks = <&mux0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			reg = <2 3>;

			clocks = <&mux0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

		cpu2: PowerPC,e6500@4 {

			device_type = "cpu";

			reg = <4 5>;

			clocks = <&mux0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

		cpu3: PowerPC,e6500@6 {

			device_type = "cpu";

			reg = <6 7>;

			clocks = <&mux0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

arch/powerpc/boot/dts/fsl/b4si-post.dtsi

+0 −15
Original line number Diff line number Diff line
@@ -398,21 +398,6 @@ 
	};



/include/ "qoriq-clockgen2.dtsi"

	clockgen: global-utilities@e1000 {

		compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";

		reg = <0xe1000 0x1000>;



		mux0: mux0@0 {

			#clock-cells = <0>;

			reg = <0x0 0x4>;

			compatible = "fsl,qoriq-core-mux-2.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,

				<&pll1 0>, <&pll1 1>, <&pll1 2>;

			clock-names = "pll0", "pll0-div2", "pll0-div4",

				"pll1", "pll1-div2", "pll1-div4";

			clock-output-names = "cmux0";

		};

	};



	rcpm: global-utilities@e2000 {

		compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";

arch/powerpc/boot/dts/fsl/p2041si-post.dtsi

+0 −18
Original line number Diff line number Diff line
@@ -327,24 +327,6 @@ 
/include/ "qoriq-clockgen1.dtsi"

	global-utilities@e1000 {

		compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";



		mux2: mux2@40 {

			#clock-cells = <0>;

			reg = <0x40 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux2";

		};



		mux3: mux3@60 {

			#clock-cells = <0>;

			reg = <0x60 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux3";

		};

	};



	rcpm: global-utilities@e2000 {

arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ 
		cpu0: PowerPC,e500mc@0 {

			device_type = "cpu";

			reg = <0>;

			clocks = <&mux0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&L2_0>;

			fsl,portid-mapping = <0x80000000>;

			L2_0: l2-cache {
@@ -99,7 +99,7 @@ 
		cpu1: PowerPC,e500mc@1 {

			device_type = "cpu";

			reg = <1>;

			clocks = <&mux1>;

			clocks = <&clockgen 1 1>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x40000000>;

			L2_1: l2-cache {
@@ -109,7 +109,7 @@ 
		cpu2: PowerPC,e500mc@2 {

			device_type = "cpu";

			reg = <2>;

			clocks = <&mux2>;

			clocks = <&clockgen 1 2>;

			next-level-cache = <&L2_2>;

			fsl,portid-mapping = <0x20000000>;

			L2_2: l2-cache {
@@ -119,7 +119,7 @@ 
		cpu3: PowerPC,e500mc@3 {

			device_type = "cpu";

			reg = <3>;

			clocks = <&mux3>;

			clocks = <&clockgen 1 3>;

			next-level-cache = <&L2_3>;

			fsl,portid-mapping = <0x10000000>;

			L2_3: l2-cache {

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