drm/radeon: also try GART for CPU accessed buffers

	rbo = container_of(bo, struct radeon_bo, tbo);

	radeon_bo_check_tiling(rbo, 0, 0);

	rdev = rbo->rdev;

	if (bo->mem.mem_type == TTM_PL_VRAM) {

	if (bo->mem.mem_type != TTM_PL_VRAM)

		return 0;

	size = bo->mem.num_pages << PAGE_SHIFT;

	offset = bo->mem.start << PAGE_SHIFT;

		if ((offset + size) > rdev->mc.visible_vram_size) {

	if ((offset + size) <= rdev->mc.visible_vram_size)

		return 0;

	/* hurrah the memory is not visible ! */

	radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);

	rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;

	r = ttm_bo_validate(bo, &rbo->placement, false, false);

			if (unlikely(r != 0))

	if (unlikely(r == -ENOMEM)) {

		radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);

		return ttm_bo_validate(bo, &rbo->placement, false, false);

	} else if (unlikely(r != 0)) {

		return r;

	}

	offset = bo->mem.start << PAGE_SHIFT;

			/* this should not happen */

	/* this should never happen */

	if ((offset + size) > rdev->mc.visible_vram_size)

		return -EINVAL;

		}

	}

	return 0;

}