Commit 5428bf5a authored May 21, 2018 by Arkadiusz Hiler Committed by Paulo Zanoni Jun 01, 2018

drm/i915/icl: Calculate link clock using the new registers



Start using the new registers for ICL and on.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-13-paulo.r.zanoni@intel.com

parent 51c83cfa

drivers/gpu/drm/i915/intel_ddi.c

+7 −2

Original line number	Diff line number	Diff line
		@@ -1345,8 +1345,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
		uint32_t cfgcr0, cfgcr1;
		uint32_t p0, p1, p2, dco_freq, ref_clock;

		if (INTEL_GEN(dev_priv) >= 11) {
		cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
		cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
		} else {
		cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
		cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
		}

		p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
		p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;

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