Commit 541d284b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm[64] perf updates from Will Deacon:
 "In the past, I have funnelled perf updates through the respective
  architecture trees, but now that the arm/arm64 perf driver has been
  largely consolidated under drivers/perf/, it makes more sense to send
  a separate pull, particularly as I'm listed as maintainer for all the
  files involved.  I offered the branch to arm-soc, but Arnd suggested
  that I just send it to you directly.

  So, here is the arm/arm64 perf queue for 4.5.  The main features are
  described below, but the most useful change is from Drew, which
  advertises our architected event mapping in sysfs so that the perf
  tool is a lot more user friendly and no longer requires the use of
  magic hex constants for profiling common events.

   - Support for the CPU PMU in Cortex-A72

   - Add sysfs entries to describe the architected events and their
     mappings for PMUv{1-3}"

* tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: perf: add support for Cortex-A72
  arm64: perf: add format entry to describe event -> config mapping
  ARM: perf: add format entry to describe event -> config mapping
  arm64: kernel: enforce pmuserenr_el0 initialization and restore
  arm64: perf: Correct Cortex-A53/A57 compatible values
  arm64: perf: Add event descriptions
  arm64: perf: Convert event enums to #defines
  arm: perf: Add event descriptions
  arm: perf: Convert event enums to #defines
  drivers/perf: kill armpmu_register
parents fa5fd7c6 5d7ee877

Documentation/devicetree/bindings/arm/pmu.txt

+3 −2
Original line number Diff line number Diff line
@@ -9,8 +9,9 @@ Required properties: 
- compatible : should be one of

	"apm,potenza-pmu"

	"arm,armv8-pmuv3"

	"arm.cortex-a57-pmu"

	"arm.cortex-a53-pmu"

	"arm,cortex-a72-pmu"

	"arm,cortex-a57-pmu"

	"arm,cortex-a53-pmu"

	"arm,cortex-a17-pmu"

	"arm,cortex-a15-pmu"

	"arm,cortex-a12-pmu"

arch/arm/kernel/perf_event_v7.c

+220 −101
Original line number Diff line number Diff line
@@ -35,19 +35,18 @@ 
 * but the encodings are considered to be `reserved' in the case that

 * they are not available.

 */

enum armv7_perf_types {

	ARMV7_PERFCTR_PMNC_SW_INCR			= 0x00,

	ARMV7_PERFCTR_L1_ICACHE_REFILL			= 0x01,

	ARMV7_PERFCTR_ITLB_REFILL			= 0x02,

	ARMV7_PERFCTR_L1_DCACHE_REFILL			= 0x03,

	ARMV7_PERFCTR_L1_DCACHE_ACCESS			= 0x04,

	ARMV7_PERFCTR_DTLB_REFILL			= 0x05,

	ARMV7_PERFCTR_MEM_READ				= 0x06,

	ARMV7_PERFCTR_MEM_WRITE				= 0x07,

	ARMV7_PERFCTR_INSTR_EXECUTED			= 0x08,

	ARMV7_PERFCTR_EXC_TAKEN				= 0x09,

	ARMV7_PERFCTR_EXC_EXECUTED			= 0x0A,

	ARMV7_PERFCTR_CID_WRITE				= 0x0B,

#define ARMV7_PERFCTR_PMNC_SW_INCR			0x00

#define ARMV7_PERFCTR_L1_ICACHE_REFILL			0x01

#define ARMV7_PERFCTR_ITLB_REFILL			0x02

#define ARMV7_PERFCTR_L1_DCACHE_REFILL			0x03

#define ARMV7_PERFCTR_L1_DCACHE_ACCESS			0x04

#define ARMV7_PERFCTR_DTLB_REFILL			0x05

#define ARMV7_PERFCTR_MEM_READ				0x06

#define ARMV7_PERFCTR_MEM_WRITE				0x07

#define ARMV7_PERFCTR_INSTR_EXECUTED			0x08

#define ARMV7_PERFCTR_EXC_TAKEN				0x09

#define ARMV7_PERFCTR_EXC_EXECUTED			0x0A

#define ARMV7_PERFCTR_CID_WRITE				0x0B



/*

 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
@@ -56,112 +55,97 @@ enum armv7_perf_types { 
 *  - instructions that explicitly write the PC,

 *  - exception generating instructions.

 */

	ARMV7_PERFCTR_PC_WRITE				= 0x0C,

	ARMV7_PERFCTR_PC_IMM_BRANCH			= 0x0D,

	ARMV7_PERFCTR_PC_PROC_RETURN			= 0x0E,

	ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS		= 0x0F,

	ARMV7_PERFCTR_PC_BRANCH_MIS_PRED		= 0x10,

	ARMV7_PERFCTR_CLOCK_CYCLES			= 0x11,

	ARMV7_PERFCTR_PC_BRANCH_PRED			= 0x12,

#define ARMV7_PERFCTR_PC_WRITE				0x0C

#define ARMV7_PERFCTR_PC_IMM_BRANCH			0x0D

#define ARMV7_PERFCTR_PC_PROC_RETURN			0x0E

#define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS		0x0F

#define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED		0x10

#define ARMV7_PERFCTR_CLOCK_CYCLES			0x11

#define ARMV7_PERFCTR_PC_BRANCH_PRED			0x12



/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */

	ARMV7_PERFCTR_MEM_ACCESS			= 0x13,

	ARMV7_PERFCTR_L1_ICACHE_ACCESS			= 0x14,

	ARMV7_PERFCTR_L1_DCACHE_WB			= 0x15,

	ARMV7_PERFCTR_L2_CACHE_ACCESS			= 0x16,

	ARMV7_PERFCTR_L2_CACHE_REFILL			= 0x17,

	ARMV7_PERFCTR_L2_CACHE_WB			= 0x18,

	ARMV7_PERFCTR_BUS_ACCESS			= 0x19,

	ARMV7_PERFCTR_MEM_ERROR				= 0x1A,

	ARMV7_PERFCTR_INSTR_SPEC			= 0x1B,

	ARMV7_PERFCTR_TTBR_WRITE			= 0x1C,

	ARMV7_PERFCTR_BUS_CYCLES			= 0x1D,



	ARMV7_PERFCTR_CPU_CYCLES			= 0xFF

};

#define ARMV7_PERFCTR_MEM_ACCESS			0x13

#define ARMV7_PERFCTR_L1_ICACHE_ACCESS			0x14

#define ARMV7_PERFCTR_L1_DCACHE_WB			0x15

#define ARMV7_PERFCTR_L2_CACHE_ACCESS			0x16

#define ARMV7_PERFCTR_L2_CACHE_REFILL			0x17

#define ARMV7_PERFCTR_L2_CACHE_WB			0x18

#define ARMV7_PERFCTR_BUS_ACCESS			0x19

#define ARMV7_PERFCTR_MEM_ERROR				0x1A

#define ARMV7_PERFCTR_INSTR_SPEC			0x1B

#define ARMV7_PERFCTR_TTBR_WRITE			0x1C

#define ARMV7_PERFCTR_BUS_CYCLES			0x1D



#define ARMV7_PERFCTR_CPU_CYCLES			0xFF



/* ARMv7 Cortex-A8 specific event types */

enum armv7_a8_perf_types {

	ARMV7_A8_PERFCTR_L2_CACHE_ACCESS		= 0x43,

	ARMV7_A8_PERFCTR_L2_CACHE_REFILL		= 0x44,

	ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS		= 0x50,

	ARMV7_A8_PERFCTR_STALL_ISIDE			= 0x56,

};

#define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS		0x43

#define ARMV7_A8_PERFCTR_L2_CACHE_REFILL		0x44

#define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS		0x50

#define ARMV7_A8_PERFCTR_STALL_ISIDE			0x56



/* ARMv7 Cortex-A9 specific event types */

enum armv7_a9_perf_types {

	ARMV7_A9_PERFCTR_INSTR_CORE_RENAME		= 0x68,

	ARMV7_A9_PERFCTR_STALL_ICACHE			= 0x60,

	ARMV7_A9_PERFCTR_STALL_DISPATCH			= 0x66,

};

#define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME		0x68

#define ARMV7_A9_PERFCTR_STALL_ICACHE			0x60

#define ARMV7_A9_PERFCTR_STALL_DISPATCH			0x66



/* ARMv7 Cortex-A5 specific event types */

enum armv7_a5_perf_types {

	ARMV7_A5_PERFCTR_PREFETCH_LINEFILL		= 0xc2,

	ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP		= 0xc3,

};

#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL		0xc2

#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP		0xc3



/* ARMv7 Cortex-A15 specific event types */

enum armv7_a15_perf_types {

	ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ		= 0x40,

	ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE	= 0x41,

	ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ		= 0x42,

	ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE	= 0x43,

#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ		0x40

#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE	0x41

#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ		0x42

#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE	0x43



	ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ		= 0x4C,

	ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE		= 0x4D,

#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ		0x4C

#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE		0x4D



	ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ		= 0x50,

	ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE		= 0x51,

	ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ		= 0x52,

	ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE		= 0x53,

#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ		0x50

#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE		0x51

#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ		0x52

#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE		0x53



	ARMV7_A15_PERFCTR_PC_WRITE_SPEC			= 0x76,

};

#define ARMV7_A15_PERFCTR_PC_WRITE_SPEC			0x76



/* ARMv7 Cortex-A12 specific event types */

enum armv7_a12_perf_types {

	ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ		= 0x40,

	ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE	= 0x41,

#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ		0x40

#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE	0x41



	ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ		= 0x50,

	ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE		= 0x51,

#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ		0x50

#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE		0x51



	ARMV7_A12_PERFCTR_PC_WRITE_SPEC			= 0x76,

#define ARMV7_A12_PERFCTR_PC_WRITE_SPEC			0x76



	ARMV7_A12_PERFCTR_PF_TLB_REFILL			= 0xe7,

};

#define ARMV7_A12_PERFCTR_PF_TLB_REFILL			0xe7



/* ARMv7 Krait specific event types */

enum krait_perf_types {

	KRAIT_PMRESR0_GROUP0				= 0xcc,

	KRAIT_PMRESR1_GROUP0				= 0xd0,

	KRAIT_PMRESR2_GROUP0				= 0xd4,

	KRAIT_VPMRESR0_GROUP0				= 0xd8,

#define KRAIT_PMRESR0_GROUP0				0xcc

#define KRAIT_PMRESR1_GROUP0				0xd0

#define KRAIT_PMRESR2_GROUP0				0xd4

#define KRAIT_VPMRESR0_GROUP0				0xd8



	KRAIT_PERFCTR_L1_ICACHE_ACCESS			= 0x10011,

	KRAIT_PERFCTR_L1_ICACHE_MISS			= 0x10010,

#define KRAIT_PERFCTR_L1_ICACHE_ACCESS			0x10011

#define KRAIT_PERFCTR_L1_ICACHE_MISS			0x10010



	KRAIT_PERFCTR_L1_ITLB_ACCESS			= 0x12222,

	KRAIT_PERFCTR_L1_DTLB_ACCESS			= 0x12210,

};

#define KRAIT_PERFCTR_L1_ITLB_ACCESS			0x12222

#define KRAIT_PERFCTR_L1_DTLB_ACCESS			0x12210



/* ARMv7 Scorpion specific event types */

enum scorpion_perf_types {

	SCORPION_LPM0_GROUP0				= 0x4c,

	SCORPION_LPM1_GROUP0				= 0x50,

	SCORPION_LPM2_GROUP0				= 0x54,

	SCORPION_L2LPM_GROUP0				= 0x58,

	SCORPION_VLPM_GROUP0				= 0x5c,

#define SCORPION_LPM0_GROUP0				0x4c

#define SCORPION_LPM1_GROUP0				0x50

#define SCORPION_LPM2_GROUP0				0x54

#define SCORPION_L2LPM_GROUP0				0x58

#define SCORPION_VLPM_GROUP0				0x5c



	SCORPION_ICACHE_ACCESS				= 0x10053,

	SCORPION_ICACHE_MISS				= 0x10052,

#define SCORPION_ICACHE_ACCESS				0x10053

#define SCORPION_ICACHE_MISS				0x10052



	SCORPION_DTLB_ACCESS				= 0x12013,

	SCORPION_DTLB_MISS				= 0x12012,

#define SCORPION_DTLB_ACCESS				0x12013

#define SCORPION_DTLB_MISS				0x12012



	SCORPION_ITLB_MISS				= 0x12021,

};

#define SCORPION_ITLB_MISS				0x12021



/*

 * Cortex-A8 HW events mapping
@@ -547,6 +531,134 @@ static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

};



PMU_FORMAT_ATTR(event, "config:0-7");



static struct attribute *armv7_pmu_format_attrs[] = {

	&format_attr_event.attr,

	NULL,

};



static struct attribute_group armv7_pmu_format_attr_group = {

	.name = "format",

	.attrs = armv7_pmu_format_attrs,

};



#define ARMV7_EVENT_ATTR_RESOLVE(m) #m

#define ARMV7_EVENT_ATTR(name, config) \

	PMU_EVENT_ATTR_STRING(name, armv7_event_attr_##name, \

			      "event=" ARMV7_EVENT_ATTR_RESOLVE(config))



ARMV7_EVENT_ATTR(sw_incr, ARMV7_PERFCTR_PMNC_SW_INCR);

ARMV7_EVENT_ATTR(l1i_cache_refill, ARMV7_PERFCTR_L1_ICACHE_REFILL);

ARMV7_EVENT_ATTR(l1i_tlb_refill, ARMV7_PERFCTR_ITLB_REFILL);

ARMV7_EVENT_ATTR(l1d_cache_refill, ARMV7_PERFCTR_L1_DCACHE_REFILL);

ARMV7_EVENT_ATTR(l1d_cache, ARMV7_PERFCTR_L1_DCACHE_ACCESS);

ARMV7_EVENT_ATTR(l1d_tlb_refill, ARMV7_PERFCTR_DTLB_REFILL);

ARMV7_EVENT_ATTR(ld_retired, ARMV7_PERFCTR_MEM_READ);

ARMV7_EVENT_ATTR(st_retired, ARMV7_PERFCTR_MEM_WRITE);

ARMV7_EVENT_ATTR(inst_retired, ARMV7_PERFCTR_INSTR_EXECUTED);

ARMV7_EVENT_ATTR(exc_taken, ARMV7_PERFCTR_EXC_TAKEN);

ARMV7_EVENT_ATTR(exc_return, ARMV7_PERFCTR_EXC_EXECUTED);

ARMV7_EVENT_ATTR(cid_write_retired, ARMV7_PERFCTR_CID_WRITE);

ARMV7_EVENT_ATTR(pc_write_retired, ARMV7_PERFCTR_PC_WRITE);

ARMV7_EVENT_ATTR(br_immed_retired, ARMV7_PERFCTR_PC_IMM_BRANCH);

ARMV7_EVENT_ATTR(br_return_retired, ARMV7_PERFCTR_PC_PROC_RETURN);

ARMV7_EVENT_ATTR(unaligned_ldst_retired, ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS);

ARMV7_EVENT_ATTR(br_mis_pred, ARMV7_PERFCTR_PC_BRANCH_MIS_PRED);

ARMV7_EVENT_ATTR(cpu_cycles, ARMV7_PERFCTR_CLOCK_CYCLES);

ARMV7_EVENT_ATTR(br_pred, ARMV7_PERFCTR_PC_BRANCH_PRED);



static struct attribute *armv7_pmuv1_event_attrs[] = {

	&armv7_event_attr_sw_incr.attr.attr,

	&armv7_event_attr_l1i_cache_refill.attr.attr,

	&armv7_event_attr_l1i_tlb_refill.attr.attr,

	&armv7_event_attr_l1d_cache_refill.attr.attr,

	&armv7_event_attr_l1d_cache.attr.attr,

	&armv7_event_attr_l1d_tlb_refill.attr.attr,

	&armv7_event_attr_ld_retired.attr.attr,

	&armv7_event_attr_st_retired.attr.attr,

	&armv7_event_attr_inst_retired.attr.attr,

	&armv7_event_attr_exc_taken.attr.attr,

	&armv7_event_attr_exc_return.attr.attr,

	&armv7_event_attr_cid_write_retired.attr.attr,

	&armv7_event_attr_pc_write_retired.attr.attr,

	&armv7_event_attr_br_immed_retired.attr.attr,

	&armv7_event_attr_br_return_retired.attr.attr,

	&armv7_event_attr_unaligned_ldst_retired.attr.attr,

	&armv7_event_attr_br_mis_pred.attr.attr,

	&armv7_event_attr_cpu_cycles.attr.attr,

	&armv7_event_attr_br_pred.attr.attr,

	NULL,

};



static struct attribute_group armv7_pmuv1_events_attr_group = {

	.name = "events",

	.attrs = armv7_pmuv1_event_attrs,

};



static const struct attribute_group *armv7_pmuv1_attr_groups[] = {

	&armv7_pmuv1_events_attr_group,

	&armv7_pmu_format_attr_group,

	NULL,

};



ARMV7_EVENT_ATTR(mem_access, ARMV7_PERFCTR_MEM_ACCESS);

ARMV7_EVENT_ATTR(l1i_cache, ARMV7_PERFCTR_L1_ICACHE_ACCESS);

ARMV7_EVENT_ATTR(l1d_cache_wb, ARMV7_PERFCTR_L1_DCACHE_WB);

ARMV7_EVENT_ATTR(l2d_cache, ARMV7_PERFCTR_L2_CACHE_ACCESS);

ARMV7_EVENT_ATTR(l2d_cache_refill, ARMV7_PERFCTR_L2_CACHE_REFILL);

ARMV7_EVENT_ATTR(l2d_cache_wb, ARMV7_PERFCTR_L2_CACHE_WB);

ARMV7_EVENT_ATTR(bus_access, ARMV7_PERFCTR_BUS_ACCESS);

ARMV7_EVENT_ATTR(memory_error, ARMV7_PERFCTR_MEM_ERROR);

ARMV7_EVENT_ATTR(inst_spec, ARMV7_PERFCTR_INSTR_SPEC);

ARMV7_EVENT_ATTR(ttbr_write_retired, ARMV7_PERFCTR_TTBR_WRITE);

ARMV7_EVENT_ATTR(bus_cycles, ARMV7_PERFCTR_BUS_CYCLES);



static struct attribute *armv7_pmuv2_event_attrs[] = {

	&armv7_event_attr_sw_incr.attr.attr,

	&armv7_event_attr_l1i_cache_refill.attr.attr,

	&armv7_event_attr_l1i_tlb_refill.attr.attr,

	&armv7_event_attr_l1d_cache_refill.attr.attr,

	&armv7_event_attr_l1d_cache.attr.attr,

	&armv7_event_attr_l1d_tlb_refill.attr.attr,

	&armv7_event_attr_ld_retired.attr.attr,

	&armv7_event_attr_st_retired.attr.attr,

	&armv7_event_attr_inst_retired.attr.attr,

	&armv7_event_attr_exc_taken.attr.attr,

	&armv7_event_attr_exc_return.attr.attr,

	&armv7_event_attr_cid_write_retired.attr.attr,

	&armv7_event_attr_pc_write_retired.attr.attr,

	&armv7_event_attr_br_immed_retired.attr.attr,

	&armv7_event_attr_br_return_retired.attr.attr,

	&armv7_event_attr_unaligned_ldst_retired.attr.attr,

	&armv7_event_attr_br_mis_pred.attr.attr,

	&armv7_event_attr_cpu_cycles.attr.attr,

	&armv7_event_attr_br_pred.attr.attr,

	&armv7_event_attr_mem_access.attr.attr,

	&armv7_event_attr_l1i_cache.attr.attr,

	&armv7_event_attr_l1d_cache_wb.attr.attr,

	&armv7_event_attr_l2d_cache.attr.attr,

	&armv7_event_attr_l2d_cache_refill.attr.attr,

	&armv7_event_attr_l2d_cache_wb.attr.attr,

	&armv7_event_attr_bus_access.attr.attr,

	&armv7_event_attr_memory_error.attr.attr,

	&armv7_event_attr_inst_spec.attr.attr,

	&armv7_event_attr_ttbr_write_retired.attr.attr,

	&armv7_event_attr_bus_cycles.attr.attr,

	NULL,

};



static struct attribute_group armv7_pmuv2_events_attr_group = {

	.name = "events",

	.attrs = armv7_pmuv2_event_attrs,

};



static const struct attribute_group *armv7_pmuv2_attr_groups[] = {

	&armv7_pmuv2_events_attr_group,

	&armv7_pmu_format_attr_group,

	NULL,

};



/*

 * Perf Events' indices

 */
@@ -1085,6 +1197,7 @@ static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) 
	armv7pmu_init(cpu_pmu);

	cpu_pmu->name		= "armv7_cortex_a8";

	cpu_pmu->map_event	= armv7_a8_map_event;

	cpu_pmu->pmu.attr_groups = armv7_pmuv1_attr_groups;

	return armv7_probe_num_events(cpu_pmu);

}
@@ -1093,6 +1206,7 @@ static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) 
	armv7pmu_init(cpu_pmu);

	cpu_pmu->name		= "armv7_cortex_a9";

	cpu_pmu->map_event	= armv7_a9_map_event;

	cpu_pmu->pmu.attr_groups = armv7_pmuv1_attr_groups;

	return armv7_probe_num_events(cpu_pmu);

}
@@ -1101,6 +1215,7 @@ static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) 
	armv7pmu_init(cpu_pmu);

	cpu_pmu->name		= "armv7_cortex_a5";

	cpu_pmu->map_event	= armv7_a5_map_event;

	cpu_pmu->pmu.attr_groups = armv7_pmuv1_attr_groups;

	return armv7_probe_num_events(cpu_pmu);

}
@@ -1110,6 +1225,7 @@ static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) 
	cpu_pmu->name		= "armv7_cortex_a15";

	cpu_pmu->map_event	= armv7_a15_map_event;

	cpu_pmu->set_event_filter = armv7pmu_set_event_filter;

	cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups;

	return armv7_probe_num_events(cpu_pmu);

}
@@ -1119,6 +1235,7 @@ static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) 
	cpu_pmu->name		= "armv7_cortex_a7";

	cpu_pmu->map_event	= armv7_a7_map_event;

	cpu_pmu->set_event_filter = armv7pmu_set_event_filter;

	cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups;

	return armv7_probe_num_events(cpu_pmu);

}
@@ -1128,6 +1245,7 @@ static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) 
	cpu_pmu->name		= "armv7_cortex_a12";

	cpu_pmu->map_event	= armv7_a12_map_event;

	cpu_pmu->set_event_filter = armv7pmu_set_event_filter;

	cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups;

	return armv7_probe_num_events(cpu_pmu);

}
@@ -1135,6 +1253,7 @@ static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu) 
{

	int ret = armv7_a12_pmu_init(cpu_pmu);

	cpu_pmu->name = "armv7_cortex_a17";

	cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups;

	return ret;

}

arch/arm64/kernel/perf_event.c

+209 −54

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm64/mm/proc.S

+2 −0
Original line number Diff line number Diff line
@@ -117,6 +117,7 @@ ENTRY(cpu_do_resume) 
	 */

	ubfx	x11, x11, #1, #1

	msr	oslar_el1, x11

	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0

	mov	x0, x12

	dsb	nsh		// Make sure local tlb invalidation completed

	isb
@@ -153,6 +154,7 @@ ENTRY(__cpu_setup) 
	msr	cpacr_el1, x0			// Enable FP/ASIMD

	mov	x0, #1 << 12			// Reset mdscr_el1 and disable

	msr	mdscr_el1, x0			// access to the DCC from EL0

	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0

	/*

	 * Memory region attributes for LPAE:

	 *

drivers/perf/arm_pmu.c

+6 −9
Original line number Diff line number Diff line
@@ -551,14 +551,6 @@ static void armpmu_init(struct arm_pmu *armpmu) 
	};

}



int armpmu_register(struct arm_pmu *armpmu, int type)

{

	armpmu_init(armpmu);

	pr_info("enabled with %s PMU driver, %d counters available\n",

			armpmu->name, armpmu->num_events);

	return perf_pmu_register(&armpmu->pmu, armpmu->name, type);

}



/* Set at runtime when we know what CPU type we are. */

static struct arm_pmu *__oprofile_cpu_pmu;
@@ -887,6 +879,8 @@ int arm_pmu_device_probe(struct platform_device *pdev, 
		return -ENOMEM;

	}



	armpmu_init(pmu);



	if (!__oprofile_cpu_pmu)

		__oprofile_cpu_pmu = pmu;
@@ -912,10 +906,13 @@ int arm_pmu_device_probe(struct platform_device *pdev, 
	if (ret)

		goto out_free;



	ret = armpmu_register(pmu, -1);

	ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);

	if (ret)

		goto out_destroy;



	pr_info("enabled with %s PMU driver, %d counters available\n",

			pmu->name, pmu->num_events);



	return 0;



out_destroy:

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