remove tx3912fb (541510fc) · Commits · 戴 / test

drivers/video/Kconfig

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		@@ -1645,18 +1645,6 @@ config FB_MAXINE
		DECstation series (Personal DECstation 5000/20, /25, /33, /50,
		Codename "Maxine").

		config FB_TX3912
		bool "TMPTX3912/PR31700 frame buffer support"
		depends on (FB = y) && NINO
		select FB_CFB_FILLRECT
		select FB_CFB_COPYAREA
		select FB_CFB_IMAGEBLIT
		help
		The TX3912 is a Toshiba RISC processor based on the MIPS 3900 core
		see <http://www.toshiba.com/taec/components/Generic/risc/tx3912.htm>.

		Say Y here to enable kernel support for the on-board framebuffer.

		config FB_G364
		bool "G364 frame buffer support"
		depends on (FB = y) && (MIPS_MAGNUM_4000 \|\| OLIVETTI_M700)

drivers/video/Makefile

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		@@ -103,7 +103,6 @@ obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
		obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
		obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
		obj-$(CONFIG_FB_MAXINE) += maxinefb.o
		obj-$(CONFIG_FB_TX3912) += tx3912fb.o
		obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
		obj-$(CONFIG_FB_IMX) += imxfb.o
		obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o

drivers/video/tx3912fb.c

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		/*
		* drivers/video/tx3912fb.c
		*
		* Copyright (C) 1999 Harald Koerfgen
		* Copyright (C) 2001 Steven Hill (sjhill@realitydiluted.com)
		*
		* This file is subject to the terms and conditions of the GNU General Public
		* License. See the file COPYING in the main directory of this archive for
		* more details.
		*
		* Framebuffer for LCD controller in TMPR3912/05 and PR31700 processors
		*/
		#include <linux/module.h>
		#include <linux/kernel.h>
		#include <linux/errno.h>
		#include <linux/string.h>
		#include <linux/delay.h>
		#include <linux/interrupt.h>
		#include <linux/init.h>
		#include <linux/pm.h>
		#include <linux/fb.h>
		#include <asm/io.h>
		#include <asm/bootinfo.h>
		#include <asm/uaccess.h>
		#include <asm/tx3912.h>
		#include <video/tx3912.h>

		/*
		* Frame buffer, palette and console structures
		*/
		static struct fb_info fb_info;
		static u32 cfb8[16];

		static struct fb_fix_screeninfo tx3912fb_fix __initdata = {
		.id = "tx3912fb",
		.smem_len = ((240 * 320)/2),
		.type = FB_TYPE_PACKED_PIXELS,
		.visual = FB_VISUAL_TRUECOLOR,
		.xpanstep = 1,
		.ypanstep = 1,
		.ywrapstep = 1,
		.accel = FB_ACCEL_NONE,
		};

		static struct fb_var_screeninfo tx3912fb_var = {
		.xres = 240,
		.yres = 320,
		.xres_virtual = 240,
		.yres_virtual = 320,
		.bits_per_pixel =4,
		.red = { 0, 4, 0 }, /* ??? */
		.green = { 0, 4, 0 },
		.blue = { 0, 4, 0 },
		.activate = FB_ACTIVATE_NOW,
		.width = -1,
		.height = -1,
		.pixclock = 20000,
		.left_margin = 64,
		.right_margin = 64,
		.upper_margin = 32,
		.lower_margin = 32,
		.hsync_len = 64,
		.vsync_len = 2,
		.vmode = FB_VMODE_NONINTERLACED,
		};

		/*
		* Interface used by the world
		*/
		int tx3912fb_init(void);

		static int tx3912fb_setcolreg(u_int regno, u_int red, u_int green,
		u_int blue, u_int transp,
		struct fb_info *info);

		/*
		* Macros
		*/
		#define get_line_length(xres_virtual, bpp) \
		(u_long) (((int) xres_virtual * (int) bpp + 7) >> 3)

		/*
		* Frame buffer operations structure used by console driver
		*/
		static struct fb_ops tx3912fb_ops = {
		.owner = THIS_MODULE,
		.fb_setcolreg = tx3912fb_setcolreg,
		.fb_fillrect = cfb_fillrect,
		.fb_copyarea = cfb_copyarea,
		.fb_imageblit = cfb_imageblit,
		};

		static int tx3912fb_check_var(struct fb_var_screeninfo var, struct fb_info info)
		{
		/*
		* Memory limit
		*/
		line_length =
		get_line_length(var->xres_virtual, var->bits_per_pixel);
		if ((line_length * var->yres_virtual) > info->fix.smem_len)
		return -ENOMEM;

		return 0;
		}

		static int tx3912fb_set_par(struct fb_info *info)
		{
		u_long tx3912fb_paddr = 0;

		/* Disable the video logic */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~(TX3912_VIDEO_CTRL1_ENVID \| TX3912_VIDEO_CTRL1_DISPON),
		TX3912_VIDEO_CTRL1);
		udelay(200);

		/* Set start address for DMA transfer */
		outl(tx3912fb_paddr, TX3912_VIDEO_CTRL3);

		/* Set end address for DMA transfer */
		outl((tx3912fb_paddr + tx3912fb_fix.smem_len + 1), TX3912_VIDEO_CTRL4);

		/* Set the pixel depth */
		switch (info->var.bits_per_pixel) {
		case 1:
		/* Monochrome */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~TX3912_VIDEO_CTRL1_BITSEL_MASK, TX3912_VIDEO_CTRL1);
		info->fix.visual = FB_VISUAL_MONO10;
		break;
		case 4:
		/* 4-bit gray */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~TX3912_VIDEO_CTRL1_BITSEL_MASK, TX3912_VIDEO_CTRL1);
		outl(inl(TX3912_VIDEO_CTRL1) \|
		TX3912_VIDEO_CTRL1_BITSEL_4BIT_GRAY,
		TX3912_VIDEO_CTRL1);
		info->fix.visual = FB_VISUAL_TRUECOLOR;
		break;
		case 8:
		/* 8-bit color */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~TX3912_VIDEO_CTRL1_BITSEL_MASK, TX3912_VIDEO_CTRL1);
		outl(inl(TX3912_VIDEO_CTRL1) \|
		TX3912_VIDEO_CTRL1_BITSEL_8BIT_COLOR,
		TX3912_VIDEO_CTRL1);
		info->fix.visual = FB_VISUAL_TRUECOLOR;
		break;
		case 2:
		default:
		/* 2-bit gray */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~TX3912_VIDEO_CTRL1_BITSEL_MASK, TX3912_VIDEO_CTRL1);
		outl(inl(TX3912_VIDEO_CTRL1) \|
		TX3912_VIDEO_CTRL1_BITSEL_2BIT_GRAY,
		TX3912_VIDEO_CTRL1);
		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
		break;
		}

		/* Enable the video clock */
		outl(inl(TX3912_CLK_CTRL) \| TX3912_CLK_CTRL_ENVIDCLK,
		TX3912_CLK_CTRL);

		/* Unfreeze video logic and enable DF toggle */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~(TX3912_VIDEO_CTRL1_ENFREEZEFRAME \|
		TX3912_VIDEO_CTRL1_DFMODE)
		, TX3912_VIDEO_CTRL1);
		udelay(200);

		/* Enable the video logic */
		outl(inl(TX3912_VIDEO_CTRL1) \|
		(TX3912_VIDEO_CTRL1_ENVID \| TX3912_VIDEO_CTRL1_DISPON),
		TX3912_VIDEO_CTRL1);

		info->fix.line_length = get_line_length(var->xres_virtual,
		var->bits_per_pixel);
		}

		/*
		* Set a single color register
		*/
		static int tx3912fb_setcolreg(u_int regno, u_int red, u_int green,
		u_int blue, u_int transp,
		struct fb_info *info)
		{
		if (regno > 255)
		return 1;

		if (regno < 16)
		((u32 *)(info->pseudo_palette))[regno] = ((red & 0xe000) >> 8)
		\| ((green & 0xe000) >> 11)
		\| ((blue & 0xc000) >> 14);
		return 0;
		}

		int __init tx3912fb_setup(char *options);

		/*
		* Initialization of the framebuffer
		*/
		int __init tx3912fb_init(void)
		{
		u_long tx3912fb_paddr = 0;
		int size = (info->var.bits_per_pixel == 8) ? 256 : 16;
		char *option = NULL;

		if (fb_get_options("tx3912fb", &option))
		return -ENODEV;
		tx3912fb_setup(option);

		/* Disable the video logic */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~(TX3912_VIDEO_CTRL1_ENVID \| TX3912_VIDEO_CTRL1_DISPON),
		TX3912_VIDEO_CTRL1);
		udelay(200);

		/* Set start address for DMA transfer */
		outl(tx3912fb_paddr, TX3912_VIDEO_CTRL3);

		/* Set end address for DMA transfer */
		outl((tx3912fb_paddr + tx3912fb_fix.smem_len + 1), TX3912_VIDEO_CTRL4);

		/* Set the pixel depth */
		switch (tx3912fb_var.bits_per_pixel) {
		case 1:
		/* Monochrome */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~TX3912_VIDEO_CTRL1_BITSEL_MASK, TX3912_VIDEO_CTRL1);
		tx3912fb_fix.visual = FB_VISUAL_MONO10;
		break;
		case 4:
		/* 4-bit gray */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~TX3912_VIDEO_CTRL1_BITSEL_MASK, TX3912_VIDEO_CTRL1);
		outl(inl(TX3912_VIDEO_CTRL1) \|
		TX3912_VIDEO_CTRL1_BITSEL_4BIT_GRAY,
		TX3912_VIDEO_CTRL1);
		tx3912fb_fix.visual = FB_VISUAL_TRUECOLOR;
		tx3912fb_fix.grayscale = 1;
		break;
		case 8:
		/* 8-bit color */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~TX3912_VIDEO_CTRL1_BITSEL_MASK, TX3912_VIDEO_CTRL1);
		outl(inl(TX3912_VIDEO_CTRL1) \|
		TX3912_VIDEO_CTRL1_BITSEL_8BIT_COLOR,
		TX3912_VIDEO_CTRL1);
		tx3912fb_fix.visual = FB_VISUAL_TRUECOLOR;
		break;
		case 2:
		default:
		/* 2-bit gray */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~TX3912_VIDEO_CTRL1_BITSEL_MASK, TX3912_VIDEO_CTRL1);
		outl(inl(TX3912_VIDEO_CTRL1) \|
		TX3912_VIDEO_CTRL1_BITSEL_2BIT_GRAY,
		TX3912_VIDEO_CTRL1);
		tx3912fb_fix.visual = FB_VISUAL_PSEUDOCOLOR;
		tx3912fb_fix.grayscale = 1;
		break;
		}

		/* Enable the video clock */
		outl(inl(TX3912_CLK_CTRL) \| TX3912_CLK_CTRL_ENVIDCLK,
		TX3912_CLK_CTRL);

		/* Unfreeze video logic and enable DF toggle */
		outl(inl(TX3912_VIDEO_CTRL1) &
		~(TX3912_VIDEO_CTRL1_ENFREEZEFRAME \| TX3912_VIDEO_CTRL1_DFMODE),
		TX3912_VIDEO_CTRL1);
		udelay(200);

		/* Clear the framebuffer */
		memset((void *) tx3912fb_fix.smem_start, 0xff, tx3912fb_fix.smem_len);
		udelay(200);

		/* Enable the video logic */
		outl(inl(TX3912_VIDEO_CTRL1) \|
		(TX3912_VIDEO_CTRL1_ENVID \| TX3912_VIDEO_CTRL1_DISPON),
		TX3912_VIDEO_CTRL1);

		/*
		* Memory limit
		*/
		tx3912fb_fix.line_length =
		get_line_length(tx3912fb_var.xres_virtual, tx3912fb_var.bits_per_pixel);
		if ((tx3912fb_fix.line_length * tx3912fb_var.yres_virtual) > tx3912fb_fix.smem_len)
		return -ENOMEM;

		fb_info.fbops = &tx3912fb_ops;
		fb_info.var = tx3912fb_var;
		fb_info.fix = tx3912fb_fix;
		fb_info.pseudo_palette = cfb8;
		fb_info.flags = FBINFO_DEFAULT;

		/* Clear the framebuffer */
		memset((void *) fb_info.fix.smem_start, 0xff, fb_info.fix.smem_len);
		udelay(200);

		fb_alloc_cmap(&info->cmap, size, 0);

		if (register_framebuffer(&fb_info) < 0)
		return -1;

		printk(KERN_INFO "fb%d: TX3912 frame buffer using %uKB.\n",
		fb_info.node, (u_int) (fb_info.fix.smem_len >> 10));
		return 0;
		}

		int __init tx3912fb_setup(char *options)
		{
		char *this_opt;

		if (!options \|\| !*options)
		return 0;

		while ((this_opt = strsep(&options, ","))) {
		if (!strncmp(options, "bpp:", 4))
		tx3912fb_var.bits_per_pixel = simple_strtoul(options+4, NULL, 0);
		}
		return 0;
		}

		module_init(tx3912fb_init);
		MODULE_LICENSE("GPL");

include/asm-mips/tx3912.h

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File deleted.

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include/video/tx3912.h

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		/*
		* linux/include/video/tx3912.h
		*
		* Copyright (C) 2001 Steven Hill (sjhill@realitydiluted.com)
		*
		* This file is subject to the terms and conditions of the GNU General Public
		* License. See the file COPYING in the main directory of this archive for
		* more details.
		*
		* Includes for TMPR3912/05 and PR31700 LCD controller registers
		*/
		#include <asm/tx3912.h>

		#define VidCtrl1 REG_AT(0x028)
		#define VidCtrl2 REG_AT(0x02C)
		#define VidCtrl3 REG_AT(0x030)
		#define VidCtrl4 REG_AT(0x034)
		#define VidCtrl5 REG_AT(0x038)
		#define VidCtrl6 REG_AT(0x03C)
		#define VidCtrl7 REG_AT(0x040)
		#define VidCtrl8 REG_AT(0x044)
		#define VidCtrl9 REG_AT(0x048)
		#define VidCtrl10 REG_AT(0x04C)
		#define VidCtrl11 REG_AT(0x050)
		#define VidCtrl12 REG_AT(0x054)
		#define VidCtrl13 REG_AT(0x058)
		#define VidCtrl14 REG_AT(0x05C)

		/* Video Control 1 Register */
		#define LINECNT 0xffc00000
		#define LINECNT_SHIFT 22
		#define LOADDLY BIT(21)
		#define BAUDVAL (BIT(20) \| BIT(19) \| BIT(18) \| BIT(17) \| BIT(16))
		#define BAUDVAL_SHIFT 16
		#define VIDDONEVAL (BIT(15) \| BIT(14) \| BIT(13) \| BIT(12) \| BIT(11) \| BIT(10) \| BIT(9))
		#define VIDDONEVAL_SHIFT 9
		#define ENFREEZEFRAME BIT(8)
		#define TX3912_VIDCTRL1_BITSEL_MASK 0x000000c0
		#define TX3912_VIDCTRL1_2BIT_GRAY 0x00000040
		#define TX3912_VIDCTRL1_4BIT_GRAY 0x00000080
		#define TX3912_VIDCTRL1_8BIT_COLOR 0x000000c0
		#define BITSEL_SHIFT 6
		#define DISPSPLIT BIT(5)
		#define DISP8 BIT(4)
		#define DFMODE BIT(3)
		#define INVVID BIT(2)
		#define DISPON BIT(1)
		#define ENVID BIT(0)

		/* Video Control 2 Register */
		#define VIDRATE_MASK 0xffc00000
		#define VIDRATE_SHIFT 22
		#define HORZVAL_MASK 0x001ff000
		#define HORZVAL_SHIFT 12
		#define LINEVAL_MASK 0x000001ff

		/* Video Control 3 Register */
		#define TX3912_VIDCTRL3_VIDBANK_MASK 0xfff00000
		#define TX3912_VIDCTRL3_VIDBASEHI_MASK 0x000ffff0

		/* Video Control 4 Register */
		#define TX3912_VIDCTRL4_VIDBASELO_MASK 0x000ffff0

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