Merge branch 'topic/ppc-kvm' into next (5400fc22) · Commits · 戴 / test

arch/powerpc/include/asm/hmi.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -42,4 +42,8 @@ extern void wait_for_tb_resync(void);
		static inline void wait_for_subcore_guest_exit(void) { }
		static inline void wait_for_tb_resync(void) { }
		#endif

		struct pt_regs;
		extern long hmi_handle_debugtrig(struct pt_regs *regs);

		#endif /* __ASM_PPC64_HMI_H__ */

+17 −0

Original line number	Diff line number	Diff line
		@@ -241,6 +241,7 @@
		#define H_GET_HCA_INFO 0x1B8
		#define H_GET_PERF_COUNT 0x1BC
		#define H_MANAGE_TRACE 0x1C0
		#define H_GET_CPU_CHARACTERISTICS 0x1C8
		#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
		#define H_QUERY_INT_STATE 0x1E4
		#define H_POLL_PENDING 0x1D8
		@@ -330,6 +331,17 @@
		#define H_SIGNAL_SYS_RESET_ALL_OTHERS -2
		/* >= 0 values are CPU number */

		/* H_GET_CPU_CHARACTERISTICS return values */
		#define H_CPU_CHAR_SPEC_BAR_ORI31 (1ull << 63) // IBM bit 0
		#define H_CPU_CHAR_BCCTRL_SERIALISED (1ull << 62) // IBM bit 1
		#define H_CPU_CHAR_L1D_FLUSH_ORI30 (1ull << 61) // IBM bit 2
		#define H_CPU_CHAR_L1D_FLUSH_TRIG2 (1ull << 60) // IBM bit 3
		#define H_CPU_CHAR_L1D_THREAD_PRIV (1ull << 59) // IBM bit 4

		#define H_CPU_BEHAV_FAVOUR_SECURITY (1ull << 63) // IBM bit 0
		#define H_CPU_BEHAV_L1D_FLUSH_PR (1ull << 62) // IBM bit 1
		#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ull << 61) // IBM bit 2

		/* Flag values used in H_REGISTER_PROC_TBL hcall */
		#define PROC_TABLE_OP_MASK 0x18
		#define PROC_TABLE_DEREG 0x10
		@@ -436,6 +448,11 @@ static inline unsigned int get_longbusy_msecs(int longbusy_rc)
		}
		}

		struct h_cpu_char_result {
		u64 character;
		u64 behaviour;
		};

		#endif /* __ASSEMBLY__ */
		#endif /* __KERNEL__ */
		#endif /* _ASM_POWERPC_HVCALL_H */

+14 −0

Original line number	Diff line number	Diff line
		@@ -326,4 +326,18 @@ static inline long plapr_signal_sys_reset(long cpu)
		return plpar_hcall_norets(H_SIGNAL_SYS_RESET, cpu);
		}

		static inline long plpar_get_cpu_characteristics(struct h_cpu_char_result *p)
		{
		unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
		long rc;

		rc = plpar_hcall(H_GET_CPU_CHARACTERISTICS, retbuf);
		if (rc == H_SUCCESS) {
		p->character = retbuf[0];
		p->behaviour = retbuf[1];
		}

		return rc;
		}

		#endif /* _ASM_POWERPC_PLPAR_WRAPPERS_H */

+3 −2

Original line number	Diff line number	Diff line
		@@ -431,8 +431,9 @@
		#define SPRN_LPID 0x13F /* Logical Partition Identifier */
		#endif
		#define LPID_RSVD 0x3ff /* Reserved LPID for partn switching */
		#define SPRN_HMER 0x150 /* Hardware m? error recovery */
		#define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */
		#define SPRN_HMER 0x150 /* Hypervisor maintenance exception reg */
		#define HMER_DEBUG_TRIG (1ul << (63 - 17)) /* Debug trigger */
		#define SPRN_HMEER 0x151 /* Hyp maintenance exception enable reg */
		#define SPRN_PCR 0x152 /* Processor compatibility register */
		#define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */
		#define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */

+35 −0

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		@@ -9,6 +9,41 @@
		#ifndef _ASM_POWERPC_XIVE_REGS_H
		#define _ASM_POWERPC_XIVE_REGS_H

		/*
		* "magic" Event State Buffer (ESB) MMIO offsets.
		*
		* Each interrupt source has a 2-bit state machine called ESB
		* which can be controlled by MMIO. It's made of 2 bits, P and
		* Q. P indicates that an interrupt is pending (has been sent
		* to a queue and is waiting for an EOI). Q indicates that the
		* interrupt has been triggered while pending.
		*
		* This acts as a coalescing mechanism in order to guarantee
		* that a given interrupt only occurs at most once in a queue.
		*
		* When doing an EOI, the Q bit will indicate if the interrupt
		* needs to be re-triggered.
		*
		* The following offsets into the ESB MMIO allow to read or
		* manipulate the PQ bits. They must be used with an 8-bytes
		* load instruction. They all return the previous state of the
		* interrupt (atomically).
		*
		* Additionally, some ESB pages support doing an EOI via a
		* store at 0 and some ESBs support doing a trigger via a
		* separate trigger page.
		*/
		#define XIVE_ESB_STORE_EOI 0x400 /* Store */
		#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
		#define XIVE_ESB_GET 0x800 /* Load */
		#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
		#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
		#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
		#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */

		#define XIVE_ESB_VAL_P 0x2
		#define XIVE_ESB_VAL_Q 0x1

		/*
		* Thread Management (aka "TM") registers
		*/