Commit 53f986ac authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Joerg Roedel
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dt-bindings: memory: tegra: Squash tegra20-gart into tegra20-mc 



Splitting GART and Memory Controller wasn't a good decision that was made
back in the day. Given that the GART driver wasn't ever been used by
anything in the kernel, we decided that it will be better to correct the
mistakes of the past and merge two bindings into a single one. As a result
there is a DT ABI change for the Memory Controller that allows not to
break newer kernels using older DT and not to break older kernels using
newer DT, that is done by changing the 'compatible' of the node to
'tegra20-mc-gart' and adding a new-required clock property. The new clock
property also puts the tegra20-mc binding in line with the bindings of the
later Tegra generations.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 2fc0ac18

Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt

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NVIDIA Tegra 20 GART



Required properties:

- compatible: "nvidia,tegra20-gart"

- reg: Two pairs of cells specifying the physical address and size of

  the memory controller registers and the GART aperture respectively.



Example:



	gart {

		compatible = "nvidia,tegra20-gart";

		reg = <0x7000f024 0x00000018	/* controller registers */

		       0x58000000 0x02000000>;	/* GART aperture */

	};

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt

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NVIDIA Tegra20 MC(Memory Controller)



Required properties:

- compatible : "nvidia,tegra20-mc"

- reg : Should contain 2 register ranges(address and length); see the

  example below. Note that the MC registers are interleaved with the

  GART registers, and hence must be represented as multiple ranges.

- compatible : "nvidia,tegra20-mc-gart"

- reg : Should contain 2 register ranges: physical base address and length of

  the controller's registers and the GART aperture respectively.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - mc: the module's clock input

- interrupts : Should contain MC General interrupt.

- #reset-cells : Should be 1. This cell represents memory client module ID.

  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>

  or in the TRM documentation.

- #iommu-cells: Should be 0. This cell represents the number of cells in an

  IOMMU specifier needed to encode an address. GART supports only a single

  address space that is shared by all devices, therefore no additional

  information needed for the address encoding.



Example:

	mc: memory-controller@7000f000 {

		compatible = "nvidia,tegra20-mc";

		reg = <0x7000f000 0x024

		       0x7000f03c 0x3c4>;

		interrupts = <0 77 0x04>;

		compatible = "nvidia,tegra20-mc-gart";

		reg = <0x7000f000 0x400		/* controller registers */

		       0x58000000 0x02000000>;	/* GART aperture */

		clocks = <&tegra_car TEGRA20_CLK_MC>;

		clock-names = "mc";

		interrupts = <GIC_SPI 77 0x04>;

		#reset-cells = <1>;

		#iommu-cells = <0>;

	};



	video-codec@6001a000 {

		compatible = "nvidia,tegra20-vde";

		...

		resets = <&mc TEGRA20_MC_RESET_VDE>;

		iommus = <&mc>;

	};

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