Commit 53de0a20 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Add {preemph,voltage}_max() vfuncs 



Different platforms have different max vswing/preemph settings.
Turn that into a pair vfuncs so we can decouple intel_dp.c and
intel_ddi.c further.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200512174145.3186-5-ville.syrjala@linux.intel.com


Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
parent 33520eae

drivers/gpu/drm/i915/display/intel_ddi.c

+7 −14
Original line number Diff line number Diff line
@@ -2109,10 +2109,10 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 
				     ddi_translations[level].deemphasis);

}



u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)

static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)

{

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	enum port port = encoder->port;

	enum phy phy = intel_port_to_phy(dev_priv, port);

	int n_entries;
@@ -2165,19 +2165,9 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 
 * used on all DDI platforms. Should that change we need to

 * rethink this code.

 */

u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)

static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)

{

	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {

	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:

	return DP_TRAIN_PRE_EMPH_LEVEL_3;

	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:

		return DP_TRAIN_PRE_EMPH_LEVEL_2;

	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:

		return DP_TRAIN_PRE_EMPH_LEVEL_1;

	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:

	default:

		return DP_TRAIN_PRE_EMPH_LEVEL_0;

	}

}



static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
@@ -4535,6 +4525,9 @@ intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 
	else

		intel_dig_port->dp.set_signal_levels = hsw_set_signal_levels;



	intel_dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;

	intel_dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;



	if (INTEL_GEN(dev_priv) < 12) {

		intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);

		intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);

drivers/gpu/drm/i915/display/intel_ddi.h

+0 −3
Original line number Diff line number Diff line
@@ -42,9 +42,6 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 
					 struct intel_crtc_state *crtc_state);

u32 bxt_signal_levels(struct intel_dp *intel_dp);

u32 ddi_signal_levels(struct intel_dp *intel_dp);

u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);

u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,

				 u8 voltage_swing);

int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,

				     bool enable);

void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);

drivers/gpu/drm/i915/display/intel_display_types.h

+3 −0
Original line number Diff line number Diff line
@@ -1367,6 +1367,9 @@ struct intel_dp { 
	void (*set_idle_link_train)(struct intel_dp *intel_dp);

	void (*set_signal_levels)(struct intel_dp *intel_dp);



	u8 (*preemph_max)(struct intel_dp *intel_dp);

	u8 (*voltage_max)(struct intel_dp *intel_dp);



	/* Displayport compliance testing */

	struct intel_dp_compliance compliance;

drivers/gpu/drm/i915/display/intel_dp.c

+21 −46
Original line number Diff line number Diff line
@@ -3990,58 +3990,24 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATU 
				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;

}



/* These are source-specific values. */

u8

intel_dp_voltage_max(struct intel_dp *intel_dp)

static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	enum port port = encoder->port;



	if (HAS_DDI(dev_priv))

		return intel_ddi_dp_voltage_max(encoder);

	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||

		 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A))

		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;

	else

	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;

}



u8

intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)

static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	enum port port = encoder->port;



	if (HAS_DDI(dev_priv)) {

		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||

		   (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {

		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:

			return DP_TRAIN_PRE_EMPH_LEVEL_3;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:

			return DP_TRAIN_PRE_EMPH_LEVEL_2;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:

			return DP_TRAIN_PRE_EMPH_LEVEL_1;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:

		default:

			return DP_TRAIN_PRE_EMPH_LEVEL_0;

	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;

}

	} else {

		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:

			return DP_TRAIN_PRE_EMPH_LEVEL_2;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:



static u8 intel_dp_pre_empemph_max_2(struct intel_dp *intel_dp)

{

	return DP_TRAIN_PRE_EMPH_LEVEL_2;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:

			return DP_TRAIN_PRE_EMPH_LEVEL_1;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:

		default:

			return DP_TRAIN_PRE_EMPH_LEVEL_0;

		}

}



static u8 intel_dp_pre_empemph_max_3(struct intel_dp *intel_dp)

{

	return DP_TRAIN_PRE_EMPH_LEVEL_3;

}



static void vlv_set_signal_levels(struct intel_dp *intel_dp)
@@ -8355,6 +8321,15 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, 
	else

		intel_dig_port->dp.set_signal_levels = g4x_set_signal_levels;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||

	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {

		intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3;

		intel_dig_port->dp.voltage_max = intel_dp_voltage_max_3;

	} else {

		intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2;

		intel_dig_port->dp.voltage_max = intel_dp_voltage_max_2;

	}



	intel_dig_port->dp.output_reg = output_reg;

	intel_dig_port->max_lanes = 4;

	intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);

drivers/gpu/drm/i915/display/intel_dp.h

+0 −4
Original line number Diff line number Diff line
@@ -92,10 +92,6 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 
void

intel_dp_set_signal_levels(struct intel_dp *intel_dp);

void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);

u8

intel_dp_voltage_max(struct intel_dp *intel_dp);

u8

intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,

			   u8 *link_bw, u8 *rate_select);

bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);

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