Commit 53897b4c authored by Wambui Karuga's avatar Wambui Karuga Committed by Jani Nikula
Browse files

drm/i915/vdsc: convert to struct drm_device based logging macros. 



Converts uses of the printk based drm logging macros to the new struct
drm_device based logging macros in i915/display/intel_vdsc.c.
This was done using the following coccinelle script that transforms
based on the existence of a struct drm_i915_private device:
@@
identifier fn, T;
@@

fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}

@@
identifier fn, T;
@@

fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}

Checkpatch warnings were fixed manually.

Signed-off-by: default avatarWambui Karuga <wambui.karugax@gmail.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200130083229.12889-5-wambui.karugax@gmail.com
parent 2d733850

drivers/gpu/drm/i915/display/intel_vdsc.c

+14 −14
Original line number Diff line number Diff line
@@ -518,7 +518,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		pps_val |= DSC_422_ENABLE;

	if (vdsc_cfg->vbr_enable)

		pps_val |= DSC_VBR_ENABLE;

	DRM_INFO("PPS0 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,

			       pps_val);
@@ -542,7 +542,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	/* Populate PICTURE_PARAMETER_SET_1 registers */

	pps_val = 0;

	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);

	DRM_INFO("PPS1 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,

			       pps_val);
@@ -567,7 +567,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	pps_val = 0;

	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |

		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);

	DRM_INFO("PPS2 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,

			       pps_val);
@@ -592,7 +592,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	pps_val = 0;

	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |

		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);

	DRM_INFO("PPS3 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,

			       pps_val);
@@ -617,7 +617,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	pps_val = 0;

	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |

		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);

	DRM_INFO("PPS4 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,

			       pps_val);
@@ -642,7 +642,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	pps_val = 0;

	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |

		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);

	DRM_INFO("PPS5 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,

			       pps_val);
@@ -669,7 +669,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |

		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |

		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);

	DRM_INFO("PPS6 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,

			       pps_val);
@@ -694,7 +694,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	pps_val = 0;

	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |

		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);

	DRM_INFO("PPS7 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,

			       pps_val);
@@ -719,7 +719,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	pps_val = 0;

	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |

		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);

	DRM_INFO("PPS8 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,

			       pps_val);
@@ -744,7 +744,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	pps_val = 0;

	pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |

		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);

	DRM_INFO("PPS9 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,

			       pps_val);
@@ -771,7 +771,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |

		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |

		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);

	DRM_INFO("PPS10 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,

			       pps_val);
@@ -799,7 +799,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
				   vdsc_cfg->slice_width) |

		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /

					vdsc_cfg->slice_height);

	DRM_INFO("PPS16 = 0x%08x\n", pps_val);

	drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);

	if (!is_pipe_dsc(crtc_state)) {

		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,

			       pps_val);
@@ -826,7 +826,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
		rc_buf_thresh_dword[i / 4] |=

			(u32)(vdsc_cfg->rc_buf_thresh[i] <<

			      BITS_PER_BYTE * (i % 4));

		DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,

		drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i,

			 rc_buf_thresh_dword[i / 4]);

	}

	if (!is_pipe_dsc(crtc_state)) {
@@ -883,7 +883,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
				RC_MAX_QP_SHIFT) |

			       (vdsc_cfg->rc_range_params[i].range_min_qp <<

				RC_MIN_QP_SHIFT)) << 16 * (i % 2));

		DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,

		drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i,

			 rc_range_params_dword[i / 2]);

	}

	if (!is_pipe_dsc(crtc_state)) {

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