Commit 53575aa9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM driver updates from Olof Johansson:
 "Updates of SoC-near drivers and other driver updates that makes more
  sense to take through our tree.  In this case it's involved:

   - Some Davinci driver updates that has required corresponding
     platform code changes (gpio mostly)
   - CCI bindings and a few driver updates
   - Marvell mvebu patches for PCI MSI support (could have gone through
     the PCI tree for this release, but they were acked by Bjorn for
     3.12 so we kept them through arm-soc).
   - Marvell dove switch-over to DT-based PCIe configuration
   - Misc updates for Samsung platform dmaengine drivers"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (32 commits)
  ARM: S3C24XX: add dma pdata for s3c2410, s3c2440 and s3c2442
  dmaengine: s3c24xx-dma: add support for the s3c2410 type of controller
  ARM: S3C24XX: Fix possible dma selection warning
  PCI: mvebu: make local functions static
  PCI: mvebu: add I/O access wrappers
  PCI: mvebu: Dynamically detect if the PEX link is up to enable hot plug
  ARM: mvebu: fix gated clock documentation
  ARM: dove: remove legacy pcie and clock init
  ARM: dove: switch to DT probed mbus address windows
  ARM: SAMSUNG: set s3c24xx_dma_filter for s3c64xx-spi0 device
  ARM: S3C24XX: add platform-devices for new dma driver for s3c2412 and s3c2443
  dmaengine: add driver for Samsung s3c24xx SoCs
  ARM: S3C24XX: number the dma clocks
  PCI: mvebu: add support for Marvell Dove SoCs
  PCI: mvebu: add support for reset on GPIO
  PCI: mvebu: remove subsys_initcall
  PCI: mvebu: increment nports only for registered ports
  PCI: mvebu: move clock enable before register access
  PCI: mvebu: add support for MSI
  irqchip: armada-370-xp: implement MSI support
  ...
parents d5aabbca 3316dee2

Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt

+3 −0
Original line number Diff line number Diff line
@@ -4,6 +4,8 @@ Marvell Armada 370 and Armada XP Interrupt Controller 
Required properties:

- compatible: Should be "marvell,mpic"

- interrupt-controller: Identifies the node as an interrupt controller.

- msi-controller: Identifies the node as an PCI Message Signaled

  Interrupt controller.

- #interrupt-cells: The number of cells to define the interrupts. Should be 1.

  The cell is the IRQ number
@@ -24,6 +26,7 @@ Example: 
              #address-cells = <1>;

              #size-cells = <1>;

              interrupt-controller;

              msi-controller;

              reg = <0xd0020a00 0x1d0>,

                    <0xd0021070 0x58>;

        };

Documentation/devicetree/bindings/arm/cci.txt

+56 −4
Original line number Diff line number Diff line
@@ -36,14 +36,18 @@ specific to ARM. 


	- reg

		Usage: required

		Value type: <prop-encoded-array>

		Value type: Integer cells. A register entry, expressed as a pair

			    of cells, containing base and size.

		Definition: A standard property. Specifies base physical

			    address of CCI control registers common to all

			    interfaces.



	- ranges:

		Usage: required

		Value type: <prop-encoded-array>

		Value type: Integer cells. An array of range entries, expressed

			    as a tuple of cells, containing child address,

			    parent address and the size of the region in the

			    child address space.

		Definition: A standard property. Follow rules in the ePAPR for

			    hierarchical bus addressing. CCI interfaces

			    addresses refer to the parent node addressing
@@ -74,11 +78,49 @@ specific to ARM. 


		- reg:

			Usage: required

			Value type: <prop-encoded-array>

			Value type: Integer cells. A register entry, expressed

				    as a pair of cells, containing base and

				    size.

			Definition: the base address and size of the

				    corresponding interface programming

				    registers.



	- CCI PMU node



		Parent node must be CCI interconnect node.



		A CCI pmu node must contain the following properties:



		- compatible

			Usage: required

			Value type: <string>

			Definition: must be "arm,cci-400-pmu"



		- reg:

			Usage: required

			Value type: Integer cells. A register entry, expressed

				    as a pair of cells, containing base and

				    size.

			Definition: the base address and size of the

				    corresponding interface programming

				    registers.



		- interrupts:

			Usage: required

			Value type: Integer cells. Array of interrupt specifier

				    entries, as defined in

				    ../interrupt-controller/interrupts.txt.

			Definition: list of counter overflow interrupts, one per

				    counter. The interrupts must be specified

				    starting with the cycle counter overflow

				    interrupt, followed by counter0 overflow

				    interrupt, counter1 overflow interrupt,...

				    ,counterN overflow interrupt.



				    The CCI PMU has an interrupt signal for each

				    counter. The number of interrupts must be

				    equal to the number of counters.



* CCI interconnect bus masters



	Description: masters in the device tree connected to a CCI port
@@ -144,7 +186,7 @@ Example: 
		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0 0x2c090000 0 0x1000>;

		ranges = <0x0 0x0 0x2c090000 0x6000>;

		ranges = <0x0 0x0 0x2c090000 0x10000>;



		cci_control0: slave-if@1000 {

			compatible = "arm,cci-400-ctrl-if";
@@ -163,6 +205,16 @@ Example: 
			interface-type = "ace";

			reg = <0x5000 0x1000>;

		};



		pmu@9000 {

			 compatible = "arm,cci-400-pmu";

			 reg = <0x9000 0x5000>;

			 interrupts = <0 101 4>,

				      <0 102 4>,

				      <0 103 4>,

				      <0 104 4>,

				      <0 105 4>;

		};

	};



This CCI node corresponds to a CCI component whose control registers sits

Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt

+8 −6
Original line number Diff line number Diff line 
* Gated Clock bindings for Marvell Orion SoCs

* Gated Clock bindings for Marvell EBU SoCs



Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save

some power. The clock consumer should specify the desired clock by having

the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to

the corresponding clock gating control bit in HW to ease manual clock lookup

in datasheet.

Marvell Armada 370/XP, Dove and Kirkwood allow some peripheral clocks to be

gated to save some power. The clock consumer should specify the desired clock

by having the clock ID in its "clocks" phandle cell. The clock ID is directly

mapped to the corresponding clock gating control bit in HW to ease manual clock

lookup in datasheet.



The following is a list of provided IDs for Armada 370:

ID	Clock	Peripheral
@@ -94,6 +94,8 @@ ID Clock Peripheral 


Required properties:

- compatible : shall be one of the following:

	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating

	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating

	"marvell,dove-gating-clock" - for Dove SoC clock gating

	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating

- reg : shall be the register address of the Clock Gating Control register

Documentation/devicetree/bindings/pci/mvebu-pci.txt

+10 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ Mandatory properties: 
- compatible: one of the following values:

    marvell,armada-370-pcie

    marvell,armada-xp-pcie

    marvell,dove-pcie

    marvell,kirkwood-pcie

- #address-cells, set to <3>

- #size-cells, set to <2>
@@ -14,6 +15,8 @@ Mandatory properties: 
- ranges: ranges describing the MMIO registers to control the PCIe

  interfaces, and ranges describing the MBus windows needed to access

  the memory and I/O regions of each PCIe interface.

- msi-parent: Link to the hardware entity that serves as the Message

  Signaled Interrupt controller for this PCI controller.



The ranges describing the MMIO registers have the following layout:
@@ -74,6 +77,8 @@ and the following optional properties: 
- marvell,pcie-lane: the physical PCIe lane number, for ports having

  multiple lanes. If this property is not found, we assume that the

  value is 0.

- reset-gpios: optional gpio to PERST#

- reset-delay-us: delay in us to wait after reset de-assertion



Example:
@@ -86,6 +91,7 @@ pcie-controller { 
	#size-cells = <2>;



	bus-range = <0x00 0xff>;

	msi-parent = <&mpic>;



	ranges =

	       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000	/* Port 0.0 registers */
@@ -135,6 +141,10 @@ pcie-controller { 
		interrupt-map = <0 0 0 0 &mpic 58>;

		marvell,pcie-port = <0>;

		marvell,pcie-lane = <0>;

		/* low-active PERST# reset on GPIO 25 */

		reset-gpios = <&gpio0 25 1>;

		/* wait 20ms for device settle after reset deassertion */

		reset-delay-us = <20000>;

		clocks = <&gateclk 5>;

		status = "disabled";

	};

arch/arm/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -826,7 +826,6 @@ config ARCH_DAVINCI 
	select GENERIC_CLOCKEVENTS

	select GENERIC_IRQ_CHIP

	select HAVE_IDE

	select NEED_MACH_GPIO_H

	select TI_PRIV_EDMA

	select USE_OF

	select ZONE_DMA

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