Commit 5334df3a authored Nov 04, 2020 by Sylwester Nawrocki Committed by Krzysztof Kozlowski Nov 10, 2020

ARM: dts: exynos: Add interconnect properties to Exynos4412 bus nodes



This patch adds the following properties for Exynos4412 interconnect
bus nodes:
 - interconnects: to declare connections between nodes in order to
   guarantee PM QoS requirements between nodes,
 - #interconnect-cells: required by the interconnect framework,
 - samsung,data-clk-ratio: which allows to specify minimum data clock
   frequency corresponding to requested bandwidth for each bus.

Note that #interconnect-cells is always zero and node IDs are not
hardcoded anywhere.

Signed-off-by: Artur Świgoń <a.swigon@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20201104103657.18007-6-s.nawrocki@samsung.com


Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

parent 2024b130

arch/arm/boot/dts/exynos4412.dtsi

+6 −0

Original line number	Diff line number	Diff line
		@@ -383,6 +383,8 @@
		clocks = <&clock CLK_DIV_DMC>;
		clock-names = "bus";
		operating-points-v2 = <&bus_dmc_opp_table>;
		samsung,data-clock-ratio = <4>;
		#interconnect-cells = <0>;
		status = "disabled";
		};

		@@ -450,6 +452,8 @@
		clocks = <&clock CLK_DIV_GDL>;
		clock-names = "bus";
		operating-points-v2 = <&bus_leftbus_opp_table>;
		interconnects = <&bus_dmc>;
		#interconnect-cells = <0>;
		status = "disabled";
		};

		@@ -466,6 +470,8 @@
		clocks = <&clock CLK_ACLK160>;
		clock-names = "bus";
		operating-points-v2 = <&bus_display_opp_table>;
		interconnects = <&bus_leftbus &bus_dmc>;
		#interconnect-cells = <0>;
		status = "disabled";
		};

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