Commit 533369b1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'timers-core-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull timers and timekeeping updates from Thomas Gleixner:
 "Core:

   - Robustness improvements for the NOHZ tick management

   - Fixes and consolidation of the NTP/RTC synchronization code

   - Small fixes and improvements in various places

   - A set of function documentation udpates and fixes

   Drivers:

   - Cleanups and improvements in various clocksoure/event drivers

   - Removal of the EZChip NPS clocksource driver as the platfrom
     support was removed from ARC

   - The usual set of new device tree binding and json conversions

   - The RTC driver which have been acked by the RTC maintainer:

       * fix a long standing bug in the MC146818 library code which can
         cause reading garbage during the RTC internal update.

       * changes related to the NTP/RTC consolidation work"

* tag 'timers-core-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (46 commits)
  ntp: Fix prototype in the !CONFIG_GENERIC_CMOS_UPDATE case
  tick/sched: Make jiffies update quick check more robust
  ntp: Consolidate the RTC update implementation
  ntp: Make the RTC sync offset less obscure
  ntp, rtc: Move rtc_set_ntp_time() to ntp code
  ntp: Make the RTC synchronization more reliable
  rtc: core: Make the sync offset default more realistic
  rtc: cmos: Make rtc_cmos sync offset correct
  rtc: mc146818: Reduce spinlock section in mc146818_set_time()
  rtc: mc146818: Prevent reading garbage
  clocksource/drivers/sh_cmt: Fix potential deadlock when calling runtime PM
  clocksource/drivers/arm_arch_timer: Correct fault programming of CNTKCTL_EL1.EVNTI
  clocksource/drivers/arm_arch_timer: Use stable count reader in erratum sne
  clocksource/drivers/dw_apb_timer_of: Add error handling if no clock available
  clocksource/drivers/riscv: Make RISCV_TIMER depends on RISCV_SBI
  clocksource/drivers/ingenic: Fix section mismatch
  clocksource/drivers/cadence_ttc: Fix memory leak in ttc_setup_clockevent()
  dt-bindings: timer: renesas: tmu: Convert to json-schema
  dt-bindings: timer: renesas: tmu: Document r8a774e1 bindings
  clocksource/drivers/orion: Add missing clk_disable_unprepare() on error path
  ...
parents 76d4acf2 3cabca87

Documentation/devicetree/bindings/timer/renesas,tmu.txt

deleted100644 → 0
+0 −49
Original line number Diff line number Diff line 
* Renesas R-Mobile/R-Car Timer Unit (TMU)



The TMU is a 32-bit timer/counter with configurable clock inputs and

programmable compare match.



Channels share hardware resources but their counter and compare match value

are independent. The TMU hardware supports up to three channels.



Required Properties:



  - compatible: must contain one or more of the following:

    - "renesas,tmu-r8a7740" for the r8a7740 TMU

    - "renesas,tmu-r8a774a1" for the r8a774A1 TMU

    - "renesas,tmu-r8a774b1" for the r8a774B1 TMU

    - "renesas,tmu-r8a774c0" for the r8a774C0 TMU

    - "renesas,tmu-r8a7778" for the r8a7778 TMU

    - "renesas,tmu-r8a7779" for the r8a7779 TMU

    - "renesas,tmu-r8a77970" for the r8a77970 TMU

    - "renesas,tmu-r8a77980" for the r8a77980 TMU

    - "renesas,tmu" for any TMU.

      This is a fallback for the above renesas,tmu-* entries



  - reg: base address and length of the registers block for the timer module.



  - interrupts: interrupt-specifier for the timer, one per channel.



  - clocks: a list of phandle + clock-specifier pairs, one for each entry

    in clock-names.

  - clock-names: must contain "fck" for the functional clock.



Optional Properties:



  - #renesas,channels: number of channels implemented by the timer, must be 2

    or 3 (if not specified the value defaults to 3).





Example: R8A7779 (R-Car H1) TMU0 node



	tmu0: timer@ffd80000 {

		compatible = "renesas,tmu-r8a7779", "renesas,tmu";

		reg = <0xffd80000 0x30>;

		interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,

			     <0 33 IRQ_TYPE_LEVEL_HIGH>,

			     <0 34 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp0_clks R8A7779_CLK_TMU0>;

		clock-names = "fck";



		#renesas,channels = <3>;

	};

Documentation/devicetree/bindings/timer/renesas,tmu.yaml

0 → 100644
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/timer/renesas,tmu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas R-Mobile/R-Car Timer Unit (TMU)



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>

  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>



description:

  The TMU is a 32-bit timer/counter with configurable clock inputs and

  programmable compare match.



  Channels share hardware resources but their counter and compare match value

  are independent. The TMU hardware supports up to three channels.



properties:

  compatible:

    items:

      - enum:

          - renesas,tmu-r8a7740  # R-Mobile A1

          - renesas,tmu-r8a774a1 # RZ/G2M

          - renesas,tmu-r8a774b1 # RZ/G2N

          - renesas,tmu-r8a774c0 # RZ/G2E

          - renesas,tmu-r8a774e1 # RZ/G2H

          - renesas,tmu-r8a7778  # R-Car M1A

          - renesas,tmu-r8a7779  # R-Car H1

          - renesas,tmu-r8a77970 # R-Car V3M

          - renesas,tmu-r8a77980 # R-Car V3H

      - const: renesas,tmu



  reg:

    maxItems: 1



  interrupts:

    minItems: 2

    maxItems: 3



  clocks:

    maxItems: 1



  clock-names:

    const: fck



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



  '#renesas,channels':

    description:

      Number of channels implemented by the timer.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [ 2, 3 ]

    default: 3



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - power-domains



if:

  not:

    properties:

      compatible:

        contains:

          enum:

            - renesas,tmu-r8a7740

            - renesas,tmu-r8a7778

            - renesas,tmu-r8a7779

then:

  required:

    - resets



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/r8a7779-clock.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/r8a7779-sysc.h>

    tmu0: timer@ffd80000 {

            compatible = "renesas,tmu-r8a7779", "renesas,tmu";

            reg = <0xffd80000 0x30>;

            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

            clocks = <&mstp0_clks R8A7779_CLK_TMU0>;

            clock-names = "fck";

            power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

            #renesas,channels = <3>;

    };

drivers/clocksource/Kconfig

+1 −11
Original line number Diff line number Diff line
@@ -275,16 +275,6 @@ config CLKSRC_TI_32K 
	  This option enables support for Texas Instruments 32.768 Hz clocksource

	  available on many OMAP-like platforms.



config CLKSRC_NPS

	bool "NPS400 clocksource driver" if COMPILE_TEST

	depends on !PHYS_ADDR_T_64BIT

	select CLKSRC_MMIO

	select TIMER_OF if OF

	help

	  NPS400 clocksource support.

	  It has a 64-bit counter with update rate up to 1000MHz.

	  This counter is accessed via couple of 32-bit memory-mapped registers.



config CLKSRC_STM32

	bool "Clocksource for STM32 SoCs" if !ARCH_STM32

	depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
@@ -654,7 +644,7 @@ config ATCPIT100_TIMER 


config RISCV_TIMER

	bool "Timer for the RISC-V platform" if COMPILE_TEST

	depends on GENERIC_SCHED_CLOCK && RISCV

	depends on GENERIC_SCHED_CLOCK && RISCV && RISCV_SBI

	select TIMER_PROBE

	select TIMER_OF

	help

drivers/clocksource/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -56,7 +56,6 @@ obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o 
obj-$(CONFIG_MTK_TIMER)		+= timer-mediatek.o

obj-$(CONFIG_CLKSRC_PISTACHIO)	+= timer-pistachio.o

obj-$(CONFIG_CLKSRC_TI_32K)	+= timer-ti-32k.o

obj-$(CONFIG_CLKSRC_NPS)	+= timer-nps.o

obj-$(CONFIG_OXNAS_RPS_TIMER)	+= timer-oxnas-rps.o

obj-$(CONFIG_OWL_TIMER)		+= timer-owl.o

obj-$(CONFIG_MILBEAUT_TIMER)	+= timer-milbeaut.o

drivers/clocksource/arm_arch_timer.c

+18 −9
Original line number Diff line number Diff line
@@ -396,10 +396,10 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned long 
	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;



	if (access == ARCH_TIMER_PHYS_ACCESS) {

		cval = evt + arch_counter_get_cntpct();

		cval = evt + arch_counter_get_cntpct_stable();

		write_sysreg(cval, cntp_cval_el0);

	} else {

		cval = evt + arch_counter_get_cntvct();

		cval = evt + arch_counter_get_cntvct_stable();

		write_sysreg(cval, cntv_cval_el0);

	}
@@ -822,15 +822,24 @@ static void arch_timer_evtstrm_enable(int divider) 


static void arch_timer_configure_evtstream(void)

{

	int evt_stream_div, pos;

	int evt_stream_div, lsb;



	/*

	 * As the event stream can at most be generated at half the frequency

	 * of the counter, use half the frequency when computing the divider.

	 */

	evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;



	/*

	 * Find the closest power of two to the divisor. If the adjacent bit

	 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).

	 */

	lsb = fls(evt_stream_div) - 1;

	if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))

		lsb++;



	/* Find the closest power of two to the divisor */

	evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;

	pos = fls(evt_stream_div);

	if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))

		pos--;

	/* enable event stream */

	arch_timer_evtstrm_enable(min(pos, 15));

	arch_timer_evtstrm_enable(max(0, min(lsb, 15)));

}



static void arch_counter_set_user_access(void)

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