Commit 52e7d46c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.7-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC fixes from Vineet Gupta:

 - Revert of ll-sc backoff retry workaround in atomics/spinlocks as
   hardware is now proven to work just fine

 - Typo fixes (Thanks Andrea Gelmini)

 - Removal of obsolete DT property (Alexey)

 - Other minor fixes

* tag 'arc-4.7-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  Revert "ARCv2: spinlock/rwlock/atomics: Delayed retry of failed SCOND with exponential backoff"
  Revert "ARCv2: spinlock/rwlock: Reset retry delay when starting a new spin-wait cycle"
  Revert "ARCv2: spinlock/rwlock/atomics: reduce 1 instruction in exponential backoff"
  ARC: don't enable DISCONTIGMEM unconditionally
  ARC: [intc-compact] simplify code for 2 priority levels
  arc: Get rid of root core-frequency property
  Fix typos
parents c8ae067f ed6aefed

arch/arc/Kconfig

+4 −27
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ config RWSEM_GENERIC_SPINLOCK 
	def_bool y



config ARCH_DISCONTIGMEM_ENABLE

	def_bool y

	def_bool n



config ARCH_FLATMEM_ENABLE

	def_bool y
@@ -186,9 +186,6 @@ if SMP 
config ARC_HAS_COH_CACHES

	def_bool n



config ARC_HAS_REENTRANT_IRQ_LV2

	def_bool n



config ARC_MCIP

	bool "ARConnect Multicore IP (MCIP) Support "

	depends on ISA_ARCV2
@@ -366,25 +363,10 @@ config NODES_SHIFT 
if ISA_ARCOMPACT



config ARC_COMPACT_IRQ_LEVELS

	bool "ARCompact IRQ Priorities: High(2)/Low(1)"

	bool "Setup Timer IRQ as high Priority"

	default n

	# Timer HAS to be high priority, for any other high priority config

	select ARC_IRQ3_LV2

	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy

	depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2



if ARC_COMPACT_IRQ_LEVELS



config ARC_IRQ3_LV2

	bool



config ARC_IRQ5_LV2

	bool



config ARC_IRQ6_LV2

	bool



endif	#ARC_COMPACT_IRQ_LEVELS

	depends on !SMP



config ARC_FPU_SAVE_RESTORE

	bool "Enable FPU state persistence across context switch"
@@ -407,11 +389,6 @@ config ARC_HAS_LLSC 
	default y

	depends on !ARC_CANT_LLSC



config ARC_STAR_9000923308

	bool "Workaround for llock/scond livelock"

	default n

	depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC



config ARC_HAS_SWAPE

	bool "Insn: SWAPE (endian-swap)"

	default y
@@ -471,7 +448,7 @@ config LINUX_LINK_BASE 


config HIGHMEM

	bool "High Memory Support"

	select DISCONTIGMEM

	select ARCH_DISCONTIGMEM_ENABLE

	help

	  With ARC 2G:2G address split, only upper 2G is directly addressable by

	  kernel. Enable this to potentially allow access to rest of 2G and PAE

arch/arc/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ libs-y += arch/arc/lib/ $(LIBGCC) 


boot		:= arch/arc/boot



#default target for make without any arguements.

#default target for make without any arguments.

KBUILD_IMAGE	:= bootpImage



all:	$(KBUILD_IMAGE)

arch/arc/boot/dts/abilis_tb100.dtsi

+0 −2
Original line number Diff line number Diff line
@@ -23,8 +23,6 @@ 




/ {

	clock-frequency		= <500000000>;	/* 500 MHZ */



	soc100 {

		bus-frequency	= <166666666>;

arch/arc/boot/dts/abilis_tb101.dtsi

+0 −2
Original line number Diff line number Diff line
@@ -23,8 +23,6 @@ 




/ {

	clock-frequency		= <500000000>;	/* 500 MHZ */



	soc100 {

		bus-frequency	= <166666666>;

arch/arc/boot/dts/axc001.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ 


/ {

	compatible = "snps,arc";

	clock-frequency = <750000000>;	/* 750 MHZ */

	#address-cells = <1>;

	#size-cells = <1>;

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