Commit 52e013d0 authored by Stephen Boyd's avatar Stephen Boyd Committed by Vinod Koul
Browse files

phy: qcom-qmp: Add support for DP in USB3+DP combo phy 



Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy
driver. We already have support for the USB3 part of the combo phy, so
most additions are for the DP phy.

Split up the qcom_qmp_phy{enable,disable}() functions into the phy init,
power on, power off, and exit functions that the common phy framework
expects so that the DP phy can add even more phy ops like
phy_calibrate() and phy_configure(). This allows us to initialize the DP
PHY and configure the AUX channel before powering on the PHY at the link
rate that was negotiated during link training.

The general design is as follows:

  1) DP controller calls phy_init() to initialize the PHY and configure
  the dp_com register region.

  2) DP controller calls phy_configure() to tune the link rate and
  voltage swing and pre-emphasis settings.

  3) DP controller calls phy_power_on() to enable the PLL and power on
  the phy.

  4) DP controller calls phy_configure() again to tune the voltage swing
  and pre-emphasis settings determind during link training.

  5) DP controller calls phy_calibrate() some number of times to change
  the aux settings if the aux channel times out during link training.

  6) DP controller calls phy_power_off() if the link rate is to be
  changed and goes back to step 2 to try again at a different link rate.

  5) DP controller calls phy_power_off() and then phy_exit() to power
  down the PHY when it is done.

The DP PHY contains a PLL that is different from the one used for the
USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk
output from the DP PLL after going through various dividers. Introduce
clk ops for these two clks that just tell the child clks what the
frequency of the pixel and link are. When the phy link rate is
configured we call clk_set_rate() to update the child clks in the
display clk controller on what rate is in use. The clk frequencies
always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or
8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or
HBR3) so we simply store the link rate and use that to calculate the clk
frequencies.

The PLL enable sequence is a little different from other QMP phy PLLs so
we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called
from phy_power_on(). This should probably be split out better so that
each phy has a way to run the final PLL/PHY enable sequence.

This code is based on a submission of this phy and PLL in the drm
subsystem.

Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org
Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent f385b731

drivers/phy/qualcomm/phy-qcom-qmp.c

+695 −90

File changed.

Preview size limit exceeded, changes collapsed.

drivers/phy/qualcomm/phy-qcom-qmp.h

+80 −0
Original line number Diff line number Diff line
@@ -137,6 +137,9 @@ 
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL			0x1c



/* Only for QMP V3 PHY - QSERDES COM registers */

#define QSERDES_V3_COM_ATB_SEL1				0x000

#define QSERDES_V3_COM_ATB_SEL2				0x004

#define QSERDES_V3_COM_FREQ_UPDATE			0x008

#define QSERDES_V3_COM_BG_TIMER				0x00c

#define QSERDES_V3_COM_SSC_EN_CENTER			0x010

#define QSERDES_V3_COM_SSC_ADJ_PER1			0x014
@@ -146,6 +149,13 @@ 
#define QSERDES_V3_COM_SSC_STEP_SIZE1			0x024

#define QSERDES_V3_COM_SSC_STEP_SIZE2			0x028

#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN		0x034

# define QSERDES_V3_COM_BIAS_EN				0x0001

# define QSERDES_V3_COM_BIAS_EN_MUX			0x0002

# define QSERDES_V3_COM_CLKBUF_R_EN			0x0004

# define QSERDES_V3_COM_CLKBUF_L_EN			0x0008

# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL		0x0010

# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L		0x0020

# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R		0x0040

#define QSERDES_V3_COM_CLK_ENABLE1			0x038

#define QSERDES_V3_COM_SYS_CLK_CTRL			0x03c

#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE		0x040
@@ -207,12 +217,36 @@ 
#define QSERDES_V3_COM_CMN_MODE				0x184



/* Only for QMP V3 PHY - TX registers */

#define QSERDES_V3_TX_BIST_MODE_LANENO			0x000

#define QSERDES_V3_TX_CLKBUF_ENABLE			0x008

#define QSERDES_V3_TX_TX_EMP_POST1_LVL			0x00c

# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK		0x001f

# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN		0x0020



#define QSERDES_V3_TX_TX_DRV_LVL			0x01c

# define DP_PHY_TXn_TX_DRV_LVL_MASK			0x001f

# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN			0x0020



#define QSERDES_V3_TX_RESET_TSYNC_EN			0x024

#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN		0x028



#define QSERDES_V3_TX_TX_BAND				0x02c

#define QSERDES_V3_TX_SLEW_CNTL				0x030

#define QSERDES_V3_TX_INTERFACE_SELECT			0x034

#define QSERDES_V3_TX_RES_CODE_LANE_TX			0x03c

#define QSERDES_V3_TX_RES_CODE_LANE_RX			0x040

#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX		0x044

#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX		0x048

#define QSERDES_V3_TX_DEBUG_BUS_SEL			0x058

#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN		0x05c

#define QSERDES_V3_TX_HIGHZ_DRVR_EN			0x060

#define QSERDES_V3_TX_TX_POL_INV			0x064

#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN	0x068

#define QSERDES_V3_TX_LANE_MODE_1			0x08c

#define QSERDES_V3_TX_RCV_DETECT_LVL_2			0x0a4

#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN			0x0c0

#define QSERDES_V3_TX_TX_INTERFACE_MODE			0x0c4

#define QSERDES_V3_TX_VMODE_CTRL1			0x0f0



/* Only for QMP V3 PHY - RX registers */

#define QSERDES_V3_RX_UCDR_FO_GAIN			0x008
@@ -315,6 +349,52 @@ 
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4		0x5c

#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5		0x60



/* Only for QMP V3 PHY - DP PHY registers */

#define QSERDES_V3_DP_PHY_REVISION_ID0			0x000

#define QSERDES_V3_DP_PHY_REVISION_ID1			0x004

#define QSERDES_V3_DP_PHY_REVISION_ID2			0x008

#define QSERDES_V3_DP_PHY_REVISION_ID3			0x00c

#define QSERDES_V3_DP_PHY_CFG				0x010

#define QSERDES_V3_DP_PHY_PD_CTL			0x018

# define DP_PHY_PD_CTL_PWRDN				0x001

# define DP_PHY_PD_CTL_PSR_PWRDN			0x002

# define DP_PHY_PD_CTL_AUX_PWRDN			0x004

# define DP_PHY_PD_CTL_LANE_0_1_PWRDN			0x008

# define DP_PHY_PD_CTL_LANE_2_3_PWRDN			0x010

# define DP_PHY_PD_CTL_PLL_PWRDN			0x020

# define DP_PHY_PD_CTL_DP_CLAMP_EN			0x040

#define QSERDES_V3_DP_PHY_MODE				0x01c

#define QSERDES_V3_DP_PHY_AUX_CFG0			0x020

#define QSERDES_V3_DP_PHY_AUX_CFG1			0x024

#define QSERDES_V3_DP_PHY_AUX_CFG2			0x028

#define QSERDES_V3_DP_PHY_AUX_CFG3			0x02c

#define QSERDES_V3_DP_PHY_AUX_CFG4			0x030

#define QSERDES_V3_DP_PHY_AUX_CFG5			0x034

#define QSERDES_V3_DP_PHY_AUX_CFG6			0x038

#define QSERDES_V3_DP_PHY_AUX_CFG7			0x03c

#define QSERDES_V3_DP_PHY_AUX_CFG8			0x040

#define QSERDES_V3_DP_PHY_AUX_CFG9			0x044



#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK		0x048

# define PHY_AUX_STOP_ERR_MASK				0x01

# define PHY_AUX_DEC_ERR_MASK				0x02

# define PHY_AUX_SYNC_ERR_MASK				0x04

# define PHY_AUX_ALIGN_ERR_MASK				0x08

# define PHY_AUX_REQ_ERR_MASK				0x10



#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR		0x04c

#define QSERDES_V3_DP_PHY_AUX_BIST_CFG			0x050



#define QSERDES_V3_DP_PHY_VCO_DIV			0x064

#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL		0x06c

#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL		0x088



#define QSERDES_V3_DP_PHY_SPARE0			0x0ac

#define DP_PHY_SPARE0_MASK				0x0f

#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT		0x04(0x0004)



#define QSERDES_V3_DP_PHY_STATUS			0x0c0



/* Only for QMP V4 PHY - QSERDES COM registers */

#define QSERDES_V4_COM_SSC_EN_CENTER			0x010

#define QSERDES_V4_COM_SSC_PER1				0x01c

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