PCI: tegra: Process pending DLL transactions before entering L1 or L2 (52db2fd8) · Commits · 戴 / test

PM message are truncated while entering L1 or L2, which is resulting in receiver errors. Set the required bit to finish processing DLLP before link enter L1 or L2. Signed-off-by:

Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by:

Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by:

Thierry Reding <treding@nvidia.com>

drivers/pci/controller/pci-tegra.c

+11 −0

Original line number	Diff line number	Diff line
		@@ -212,6 +212,9 @@
		#define RP_VEND_CTL1 0x00000f48
		#define RP_VEND_CTL1_ERPT (1 << 13)

		#define RP_VEND_XP_BIST 0x00000f4c
		#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28)

		#define RP_VEND_CTL2 0x00000fa8
		#define RP_VEND_CTL2_PCA_ENABLE (1 << 7)

		@@ -538,6 +541,14 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
		value \|= RP_VEND_XP_OPPORTUNISTIC_ACK;
		value \|= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
		writel(value, port->base + RP_VEND_XP);

		/*
		* LTSSM will wait for DLLP to finish before entering L1 or L2,
		* to avoid truncation of PM messages which results in receiver errors
		*/
		value = readl(port->base + RP_VEND_XP_BIST);
		value \|= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
		writel(value, port->base + RP_VEND_XP_BIST);
		}

		static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)

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