drm/i915/tgl: Add Wa_1409085225, Wa_14010229206 (52c2e4e6) · Commits · 戴 / test

Disable Push Constant buffer addition for TGL. v2: typos, add additional Wa reference v3: use REG_BIT macro, move to rcs_engine_wa_init, clean up commit message. Bspec: 52890 Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by:

Matt Roper <matthew.d.roper@intel.com> Signed-off-by:

Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:

José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-3-jose.souza@intel.com

drivers/gpu/drm/i915/gt/intel_workarounds.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -1363,6 +1363,12 @@ rcs_engine_wa_init(struct intel_engine_cs engine, struct i915_wa_list wal)
		wa_masked_en(wal,
		GEN7_ROW_CHICKEN2,
		GEN12_DISABLE_EARLY_READ);

		/*
		* Wa_1409085225:tgl
		* Wa_14010229206:tgl
		*/
		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
		}

		if (IS_TIGERLAKE(i915)) {

drivers/gpu/drm/i915/i915_reg.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -9149,6 +9149,9 @@ enum {
		#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
		#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)

		#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
		#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)

		#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
		#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)

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