Commit 5298166d authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
Browse files

arm64: tegra: Add CPU cache topology for Tegra186 



Tegra186 has two CPU clusters with its own cache hierarchy. This patch
adds them with the cache information of each of the CPUs.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent c4502cc3

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+60 −0
Original line number Diff line number Diff line
@@ -1128,38 +1128,98 @@ 
		cpu@0 {

			compatible = "nvidia,tegra186-denver";

			device_type = "cpu";

			i-cache-size = <0x20000>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <0x10000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_DENVER>;

			reg = <0x000>;

		};



		cpu@1 {

			compatible = "nvidia,tegra186-denver";

			device_type = "cpu";

			i-cache-size = <0x20000>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <0x10000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_DENVER>;

			reg = <0x001>;

		};



		cpu@2 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_A57>;

			reg = <0x100>;

		};



		cpu@3 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_A57>;

			reg = <0x101>;

		};



		cpu@4 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_A57>;

			reg = <0x102>;

		};



		cpu@5 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_A57>;

			reg = <0x103>;

		};



		L2_DENVER: l2-cache0 {

			compatible = "cache";

			cache-unified;

			cache-level = <2>;

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;

		};



		L2_A57: l2-cache1 {

			compatible = "cache";

			cache-unified;

			cache-level = <2>;

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;

		};

	};



	bpmp: bpmp {

CRA Git | Maintained and supported by SUSTech CRA and CCSE