Commit 5296b56d authored by Guennadi Liakhovetski's avatar Guennadi Liakhovetski Committed by Dan Williams
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i.MX31: Image Processing Unit DMA and IRQ drivers 



i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.

IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.

Acked-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarGuennadi Liakhovetski <lg@denx.de>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent ef560682

arch/arm/plat-mxc/include/mach/ipu.h

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/*

 * Copyright (C) 2008

 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>

 *

 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#ifndef _IPU_H_

#define _IPU_H_



#include <linux/types.h>

#include <linux/dmaengine.h>



/* IPU DMA Controller channel definitions. */

enum ipu_channel {

	IDMAC_IC_0 = 0,		/* IC (encoding task) to memory */

	IDMAC_IC_1 = 1,		/* IC (viewfinder task) to memory */

	IDMAC_ADC_0 = 1,

	IDMAC_IC_2 = 2,

	IDMAC_ADC_1 = 2,

	IDMAC_IC_3 = 3,

	IDMAC_IC_4 = 4,

	IDMAC_IC_5 = 5,

	IDMAC_IC_6 = 6,

	IDMAC_IC_7 = 7,		/* IC (sensor data) to memory */

	IDMAC_IC_8 = 8,

	IDMAC_IC_9 = 9,

	IDMAC_IC_10 = 10,

	IDMAC_IC_11 = 11,

	IDMAC_IC_12 = 12,

	IDMAC_IC_13 = 13,

	IDMAC_SDC_0 = 14,	/* Background synchronous display data */

	IDMAC_SDC_1 = 15,	/* Foreground data (overlay) */

	IDMAC_SDC_2 = 16,

	IDMAC_SDC_3 = 17,

	IDMAC_ADC_2 = 18,

	IDMAC_ADC_3 = 19,

	IDMAC_ADC_4 = 20,

	IDMAC_ADC_5 = 21,

	IDMAC_ADC_6 = 22,

	IDMAC_ADC_7 = 23,

	IDMAC_PF_0 = 24,

	IDMAC_PF_1 = 25,

	IDMAC_PF_2 = 26,

	IDMAC_PF_3 = 27,

	IDMAC_PF_4 = 28,

	IDMAC_PF_5 = 29,

	IDMAC_PF_6 = 30,

	IDMAC_PF_7 = 31,

};



/* Order significant! */

enum ipu_channel_status {

	IPU_CHANNEL_FREE,

	IPU_CHANNEL_INITIALIZED,

	IPU_CHANNEL_READY,

	IPU_CHANNEL_ENABLED,

};



#define IPU_CHANNELS_NUM 32



enum pixel_fmt {

	/* 1 byte */

	IPU_PIX_FMT_GENERIC,

	IPU_PIX_FMT_RGB332,

	IPU_PIX_FMT_YUV420P,

	IPU_PIX_FMT_YUV422P,

	IPU_PIX_FMT_YUV420P2,

	IPU_PIX_FMT_YVU422P,

	/* 2 bytes */

	IPU_PIX_FMT_RGB565,

	IPU_PIX_FMT_RGB666,

	IPU_PIX_FMT_BGR666,

	IPU_PIX_FMT_YUYV,

	IPU_PIX_FMT_UYVY,

	/* 3 bytes */

	IPU_PIX_FMT_RGB24,

	IPU_PIX_FMT_BGR24,

	/* 4 bytes */

	IPU_PIX_FMT_GENERIC_32,

	IPU_PIX_FMT_RGB32,

	IPU_PIX_FMT_BGR32,

	IPU_PIX_FMT_ABGR32,

	IPU_PIX_FMT_BGRA32,

	IPU_PIX_FMT_RGBA32,

};



enum ipu_color_space {

	IPU_COLORSPACE_RGB,

	IPU_COLORSPACE_YCBCR,

	IPU_COLORSPACE_YUV

};



/*

 * Enumeration of IPU rotation modes

 */

enum ipu_rotate_mode {

	/* Note the enum values correspond to BAM value */

	IPU_ROTATE_NONE = 0,

	IPU_ROTATE_VERT_FLIP = 1,

	IPU_ROTATE_HORIZ_FLIP = 2,

	IPU_ROTATE_180 = 3,

	IPU_ROTATE_90_RIGHT = 4,

	IPU_ROTATE_90_RIGHT_VFLIP = 5,

	IPU_ROTATE_90_RIGHT_HFLIP = 6,

	IPU_ROTATE_90_LEFT = 7,

};



struct ipu_platform_data {

	unsigned int	irq_base;

};



/*

 * Enumeration of DI ports for ADC.

 */

enum display_port {

	DISP0,

	DISP1,

	DISP2,

	DISP3

};



struct idmac_video_param {

	unsigned short		in_width;

	unsigned short		in_height;

	uint32_t		in_pixel_fmt;

	unsigned short		out_width;

	unsigned short		out_height;

	uint32_t		out_pixel_fmt;

	unsigned short		out_stride;

	bool			graphics_combine_en;

	bool			global_alpha_en;

	bool			key_color_en;

	enum display_port	disp;

	unsigned short		out_left;

	unsigned short		out_top;

};



/*

 * Union of initialization parameters for a logical channel. So far only video

 * parameters are used.

 */

union ipu_channel_param {

	struct idmac_video_param video;

};



struct idmac_tx_desc {

	struct dma_async_tx_descriptor	txd;

	struct scatterlist		*sg;	/* scatterlist for this */

	unsigned int			sg_len;	/* tx-descriptor. */

	struct list_head		list;

};



struct idmac_channel {

	struct dma_chan		dma_chan;

	dma_cookie_t		completed;	/* last completed cookie	   */

	union ipu_channel_param	params;

	enum ipu_channel	link;	/* input channel, linked to the output	   */

	enum ipu_channel_status	status;

	void			*client;	/* Only one client per channel	   */

	unsigned int		n_tx_desc;

	struct idmac_tx_desc	*desc;		/* allocated tx-descriptors	   */

	struct scatterlist	*sg[2];	/* scatterlist elements in buffer-0 and -1 */

	struct list_head	free_list;	/* free tx-descriptors		   */

	struct list_head	queue;		/* queued tx-descriptors	   */

	spinlock_t		lock;		/* protects sg[0,1], queue	   */

	struct mutex		chan_mutex; /* protects status, cookie, free_list  */

	bool			sec_chan_en;

	int			active_buffer;

	unsigned int		eof_irq;

	char			eof_name[16];	/* EOF IRQ name for request_irq()  */

};



#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd)

#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan)



#endif

arch/arm/plat-mxc/include/mach/irqs.h

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@@ -35,7 +35,15 @@ 
#define MXC_BOARD_IRQ_START	(MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)

#define MXC_BOARD_IRQS	16



#define NR_IRQS		(MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)

#define MXC_IPU_IRQ_START	(MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)



#ifdef CONFIG_MX3_IPU_IRQS

#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS

#else

#define MX3_IPU_IRQS 0

#endif



#define NR_IRQS			(MXC_IPU_IRQ_START + MX3_IPU_IRQS)



extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);

drivers/dma/Kconfig

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@@ -62,6 +62,25 @@ config MV_XOR 
	---help---

	  Enable support for the Marvell XOR engine.



config MX3_IPU

	bool "MX3x Image Processing Unit support"

	depends on ARCH_MX3

	select DMA_ENGINE

	default y

	help

	  If you plan to use the Image Processing unit in the i.MX3x, say

	  Y here. If unsure, select Y.



config MX3_IPU_IRQS

	int "Number of dynamically mapped interrupts for IPU"

	depends on MX3_IPU

	range 2 137

	default 4

	help

	  Out of 137 interrupt sources on i.MX31 IPU only very few are used.

	  To avoid bloating the irq_desc[] array we allocate a sufficient

	  number of IRQ slots and map them dynamically to specific sources.



config DMA_ENGINE

	bool

drivers/dma/Makefile

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@@ -7,3 +7,4 @@ obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o 
obj-$(CONFIG_FSL_DMA) += fsldma.o

obj-$(CONFIG_MV_XOR) += mv_xor.o

obj-$(CONFIG_DW_DMAC) += dw_dmac.o

obj-$(CONFIG_MX3_IPU) += ipu/

drivers/dma/ipu/Makefile

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obj-y	+= ipu_irq.o ipu_idmac.o

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