Commit 52954edd authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Allocate a status page for each timeline 



Allocate a page for use as a status page by a group of timelines, as we
only need a dword of storage for each (rounded up to the cacheline for
safety) we can pack multiple timelines into the same page. Each timeline
will then be able to track its own HW seqno.

v2: Reuse the common per-engine HWSP for the solitary ringbuffer
timeline, so that we do not have to emit (using per-gen specialised
vfuncs) the breadcrumb into the distinct timeline HWSP and instead can
keep on using the common MI_STORE_DWORD_INDEX. However, to maintain the
sleight-of-hand for the global/per-context seqno switchover, we will
store both temporarily (and so use a custom offset for the shared timeline
HWSP until the switch over).

v3: Keep things simple and allocate a page for each timeline, page
sharing comes next.

v4: I was caught repeating the same MI_STORE_DWORD_IMM over and over
again in selftests.

v5: And caught red handed copying create timeline + check.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190128181812.22804-3-chris@chris-wilson.co.uk
parent b18fe4be

drivers/gpu/drm/i915/i915_timeline.c

+112 −9
Original line number Diff line number Diff line
@@ -9,28 +9,78 @@ 
#include "i915_timeline.h"

#include "i915_syncmap.h"



void i915_timeline_init(struct drm_i915_private *i915,

static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)

{

	struct drm_i915_gem_object *obj;

	struct i915_vma *vma;



	obj = i915_gem_object_create_internal(i915, PAGE_SIZE);

	if (IS_ERR(obj))

		return ERR_CAST(obj);



	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);



	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);

	if (IS_ERR(vma))

		i915_gem_object_put(obj);



	return vma;

}



static int hwsp_alloc(struct i915_timeline *timeline)

{

	struct i915_vma *vma;



	vma = __hwsp_alloc(timeline->i915);

	if (IS_ERR(vma))

		return PTR_ERR(vma);



	timeline->hwsp_ggtt = vma;

	timeline->hwsp_offset = 0;



	return 0;

}



int i915_timeline_init(struct drm_i915_private *i915,

		       struct i915_timeline *timeline,

			const char *name)

		       const char *name,

		       struct i915_vma *global_hwsp)

{

	struct i915_gt_timelines *gt = &i915->gt.timelines;

	void *vaddr;

	int err;



	/*

	 * Ideally we want a set of engines on a single leaf as we expect

	 * to mostly be tracking synchronisation between engines. It is not

	 * a huge issue if this is not the case, but we may want to mitigate

	 * any page crossing penalties if they become an issue.

	 *

	 * Called during early_init before we know how many engines there are.

	 */

	BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);



	timeline->i915 = i915;

	timeline->name = name;

	timeline->pin_count = 0;



	if (global_hwsp) {

		timeline->hwsp_ggtt = i915_vma_get(global_hwsp);

		timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR;

	} else {

		err = hwsp_alloc(timeline);

		if (err)

			return err;

	}



	mutex_lock(&gt->mutex);

	list_add(&timeline->link, &gt->list);

	mutex_unlock(&gt->mutex);

	vaddr = i915_gem_object_pin_map(timeline->hwsp_ggtt->obj, I915_MAP_WB);

	if (IS_ERR(vaddr)) {

		i915_vma_put(timeline->hwsp_ggtt);

		return PTR_ERR(vaddr);

	}



	/* Called during early_init before we know how many engines there are */

	timeline->hwsp_seqno =

		memset(vaddr + timeline->hwsp_offset, 0, CACHELINE_BYTES);



	timeline->fence_context = dma_fence_context_alloc(1);
@@ -40,6 +90,12 @@ void i915_timeline_init(struct drm_i915_private *i915, 
	INIT_LIST_HEAD(&timeline->requests);



	i915_syncmap_init(&timeline->sync);



	mutex_lock(&gt->mutex);

	list_add(&timeline->link, &gt->list);

	mutex_unlock(&gt->mutex);



	return 0;

}



void i915_timelines_init(struct drm_i915_private *i915)
@@ -85,6 +141,7 @@ void i915_timeline_fini(struct i915_timeline *timeline) 
{

	struct i915_gt_timelines *gt = &timeline->i915->gt.timelines;



	GEM_BUG_ON(timeline->pin_count);

	GEM_BUG_ON(!list_empty(&timeline->requests));



	i915_syncmap_free(&timeline->sync);
@@ -92,23 +149,69 @@ void i915_timeline_fini(struct i915_timeline *timeline) 
	mutex_lock(&gt->mutex);

	list_del(&timeline->link);

	mutex_unlock(&gt->mutex);



	i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);

	i915_vma_put(timeline->hwsp_ggtt);

}



struct i915_timeline *

i915_timeline_create(struct drm_i915_private *i915, const char *name)

i915_timeline_create(struct drm_i915_private *i915,

		     const char *name,

		     struct i915_vma *global_hwsp)

{

	struct i915_timeline *timeline;

	int err;



	timeline = kzalloc(sizeof(*timeline), GFP_KERNEL);

	if (!timeline)

		return ERR_PTR(-ENOMEM);



	i915_timeline_init(i915, timeline, name);

	err = i915_timeline_init(i915, timeline, name, global_hwsp);

	if (err) {

		kfree(timeline);

		return ERR_PTR(err);

	}



	kref_init(&timeline->kref);



	return timeline;

}



int i915_timeline_pin(struct i915_timeline *tl)

{

	int err;



	if (tl->pin_count++)

		return 0;

	GEM_BUG_ON(!tl->pin_count);



	err = i915_vma_pin(tl->hwsp_ggtt, 0, 0, PIN_GLOBAL | PIN_HIGH);

	if (err)

		goto unpin;



	return 0;



unpin:

	tl->pin_count = 0;

	return err;

}



void i915_timeline_unpin(struct i915_timeline *tl)

{

	GEM_BUG_ON(!tl->pin_count);

	if (--tl->pin_count)

		return;



	/*

	 * Since this timeline is idle, all bariers upon which we were waiting

	 * must also be complete and so we can discard the last used barriers

	 * without loss of information.

	 */

	i915_syncmap_free(&tl->sync);



	__i915_vma_unpin(tl->hwsp_ggtt);

}



void __i915_timeline_free(struct kref *kref)

{

	struct i915_timeline *timeline =

drivers/gpu/drm/i915/i915_timeline.h

+17 −4
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ 
#include "i915_syncmap.h"

#include "i915_utils.h"



struct i915_vma;



struct i915_timeline {

	u64 fence_context;

	u32 seqno;
@@ -40,6 +42,11 @@ struct i915_timeline { 
#define TIMELINE_CLIENT 0 /* default subclass */

#define TIMELINE_ENGINE 1



	unsigned int pin_count;

	const u32 *hwsp_seqno;

	struct i915_vma *hwsp_ggtt;

	u32 hwsp_offset;



	/**

	 * List of breadcrumbs associated with GPU requests currently

	 * outstanding.
@@ -71,9 +78,10 @@ struct i915_timeline { 
	struct kref kref;

};



void i915_timeline_init(struct drm_i915_private *i915,

int i915_timeline_init(struct drm_i915_private *i915,

		       struct i915_timeline *tl,

			const char *name);

		       const char *name,

		       struct i915_vma *hwsp);

void i915_timeline_fini(struct i915_timeline *tl);



static inline void
@@ -96,7 +104,9 @@ i915_timeline_set_subclass(struct i915_timeline *timeline, 
}



struct i915_timeline *

i915_timeline_create(struct drm_i915_private *i915, const char *name);

i915_timeline_create(struct drm_i915_private *i915,

		     const char *name,

		     struct i915_vma *global_hwsp);



static inline struct i915_timeline *

i915_timeline_get(struct i915_timeline *timeline)
@@ -135,6 +145,9 @@ static inline bool i915_timeline_sync_is_later(struct i915_timeline *tl, 
	return __i915_timeline_sync_is_later(tl, fence->context, fence->seqno);

}



int i915_timeline_pin(struct i915_timeline *tl);

void i915_timeline_unpin(struct i915_timeline *tl);



void i915_timelines_init(struct drm_i915_private *i915);

void i915_timelines_park(struct drm_i915_private *i915);

void i915_timelines_fini(struct drm_i915_private *i915);

drivers/gpu/drm/i915/intel_engine_cs.c

+46 −30
Original line number Diff line number Diff line
@@ -484,26 +484,6 @@ static void intel_engine_init_execlist(struct intel_engine_cs *engine) 
	execlists->queue = RB_ROOT_CACHED;

}



/**

 * intel_engines_setup_common - setup engine state not requiring hw access

 * @engine: Engine to setup.

 *

 * Initializes @engine@ structure members shared between legacy and execlists

 * submission modes which do not require hardware access.

 *

 * Typically done early in the submission mode specific engine setup stage.

 */

void intel_engine_setup_common(struct intel_engine_cs *engine)

{

	i915_timeline_init(engine->i915, &engine->timeline, engine->name);

	i915_timeline_set_subclass(&engine->timeline, TIMELINE_ENGINE);



	intel_engine_init_execlist(engine);

	intel_engine_init_hangcheck(engine);

	intel_engine_init_batch_pool(engine);

	intel_engine_init_cmd_parser(engine);

}



static void cleanup_status_page(struct intel_engine_cs *engine)

{

	struct i915_vma *vma;
@@ -601,6 +581,44 @@ err: 
	return ret;

}



/**

 * intel_engines_setup_common - setup engine state not requiring hw access

 * @engine: Engine to setup.

 *

 * Initializes @engine@ structure members shared between legacy and execlists

 * submission modes which do not require hardware access.

 *

 * Typically done early in the submission mode specific engine setup stage.

 */

int intel_engine_setup_common(struct intel_engine_cs *engine)

{

	int err;



	err = init_status_page(engine);

	if (err)

		return err;



	err = i915_timeline_init(engine->i915,

				 &engine->timeline,

				 engine->name,

				 engine->status_page.vma);

	if (err)

		goto err_hwsp;



	i915_timeline_set_subclass(&engine->timeline, TIMELINE_ENGINE);



	intel_engine_init_execlist(engine);

	intel_engine_init_hangcheck(engine);

	intel_engine_init_batch_pool(engine);

	intel_engine_init_cmd_parser(engine);



	return 0;



err_hwsp:

	cleanup_status_page(engine);

	return err;

}



static void __intel_context_unpin(struct i915_gem_context *ctx,

				  struct intel_engine_cs *engine)

{
@@ -617,7 +635,7 @@ struct measure_breadcrumb { 
static int measure_breadcrumb_dw(struct intel_engine_cs *engine)

{

	struct measure_breadcrumb *frame;

	unsigned int dw;

	int dw = -ENOMEM;



	GEM_BUG_ON(!engine->i915->gt.scratch);
@@ -625,7 +643,10 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine) 
	if (!frame)

		return -ENOMEM;



	i915_timeline_init(engine->i915, &frame->timeline, "measure");

	if (i915_timeline_init(engine->i915,

			       &frame->timeline, "measure",

			       engine->status_page.vma))

		goto out_frame;



	INIT_LIST_HEAD(&frame->ring.request_list);

	frame->ring.timeline = &frame->timeline;
@@ -642,8 +663,9 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine) 
	dw = engine->emit_breadcrumb(&frame->rq, frame->cs) - frame->cs;



	i915_timeline_fini(&frame->timeline);

	kfree(frame);



out_frame:

	kfree(frame);

	return dw;

}
@@ -693,20 +715,14 @@ int intel_engine_init_common(struct intel_engine_cs *engine) 
	if (ret)

		goto err_unpin_preempt;



	ret = init_status_page(engine);

	if (ret)

		goto err_breadcrumbs;



	ret = measure_breadcrumb_dw(engine);

	if (ret < 0)

		goto err_status_page;

		goto err_breadcrumbs;



	engine->emit_breadcrumb_dw = ret;



	return 0;



err_status_page:

	cleanup_status_page(engine);

err_breadcrumbs:

	intel_engine_fini_breadcrumbs(engine);

err_unpin_preempt:

drivers/gpu/drm/i915/intel_lrc.c

+17 −5
Original line number Diff line number Diff line
@@ -2206,10 +2206,14 @@ logical_ring_default_irqs(struct intel_engine_cs *engine) 
	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;

}



static void

static int

logical_ring_setup(struct intel_engine_cs *engine)

{

	intel_engine_setup_common(engine);

	int err;



	err = intel_engine_setup_common(engine);

	if (err)

		return err;



	/* Intentionally left blank. */

	engine->buffer = NULL;
@@ -2219,6 +2223,8 @@ logical_ring_setup(struct intel_engine_cs *engine) 


	logical_ring_default_vfuncs(engine);

	logical_ring_default_irqs(engine);



	return 0;

}



static int logical_ring_init(struct intel_engine_cs *engine)
@@ -2267,7 +2273,9 @@ int logical_render_ring_init(struct intel_engine_cs *engine) 
{

	int ret;



	logical_ring_setup(engine);

	ret = logical_ring_setup(engine);

	if (ret)

		return ret;



	/* Override some for render ring. */

	engine->init_context = gen8_init_rcs_context;
@@ -2296,7 +2304,11 @@ int logical_render_ring_init(struct intel_engine_cs *engine) 


int logical_xcs_ring_init(struct intel_engine_cs *engine)

{

	logical_ring_setup(engine);

	int err;



	err = logical_ring_setup(engine);

	if (err)

		return err;



	return logical_ring_init(engine);

}
@@ -2629,7 +2641,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, 
		goto error_deref_obj;

	}



	timeline = i915_timeline_create(ctx->i915, ctx->name);

	timeline = i915_timeline_create(ctx->i915, ctx->name, NULL);

	if (IS_ERR(timeline)) {

		ret = PTR_ERR(timeline);

		goto error_deref_obj;

drivers/gpu/drm/i915/intel_ringbuffer.c

+8 −2
Original line number Diff line number Diff line
@@ -1545,9 +1545,13 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine) 
	struct intel_ring *ring;

	int err;



	intel_engine_setup_common(engine);

	err = intel_engine_setup_common(engine);

	if (err)

		return err;



	timeline = i915_timeline_create(engine->i915, engine->name);

	timeline = i915_timeline_create(engine->i915,

					engine->name,

					engine->status_page.vma);

	if (IS_ERR(timeline)) {

		err = PTR_ERR(timeline);

		goto err;
@@ -1571,6 +1575,8 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine) 
	if (err)

		goto err_unpin;



	GEM_BUG_ON(ring->timeline->hwsp_ggtt != engine->status_page.vma);



	return 0;



err_unpin:

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