Commit 5280508e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-arm-dt2-for-v4.20' of... 

Merge tag 'renesas-arm-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Second Round of Renesas ARM Based SoC DT Updates for v4.20

* RZ/G1M (r8a7743) based iWave G20D-Q7 board and camera daughter board
  - Move PCIe node out of common dtsi to allow reuse of the common dtsi
    on the iWave RZ/G1N board
* RZ/G1C (r8a77470) SoC: Add I2C4, SDHI2 and SMP support
* R-Car Gen1 based boards and R-Car Gen2 SoCs:
  - Enhance top-of-file comments to include SoC name
* RZ/N1D (r9a06g032) SoC:
  - Correct UART0 description and add all other UARTs

* tag 'renesas-arm-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  ARM: dts: iwg20d-q7-common: Move pciec node out of common dtsi
  ARM: dts: r8a77470: Add I2C4 support
  ARM: dts: r8a77470: Add SDHI2 support
  ARM: dts: r8a77470: Add SMP support
  ARM: dts: R-Car Gen1 board comment update
  ARM: dts: Include R-Car Gen2 product name in DTSI files
  ARM: dts: r9a06g032: Correct UART and add all other UARTs

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 0526b92e e0a39511

arch/arm/boot/dts/iwg20d-q7-common.dtsi

+0 −4
Original line number Diff line number Diff line
@@ -160,10 +160,6 @@ 
	clock-frequency = <100000000>;

};



&pciec {

	status = "okay";

};



&pfc {

	can0_pins: can0 {

		groups = "can0_data_d";

arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts

+4 −0
Original line number Diff line number Diff line
@@ -14,3 +14,7 @@ 
	model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";

	compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";

};



&pciec {

	status = "okay";

};

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts

+4 −0
Original line number Diff line number Diff line
@@ -13,3 +13,7 @@ 
	model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";

	compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";

};



&pciec {

	status = "okay";

};

arch/arm/boot/dts/r8a77470.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -28,6 +29,15 @@ 
			next-level-cache = <&L2_CA7>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <1>;

			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;

			power-domains = <&sysc R8A77470_PD_CA7_CPU1>;

			next-level-cache = <&L2_CA7>;

		};



		L2_CA7: cache-controller-0 {

			compatible = "cache";
@@ -167,6 +177,12 @@ 
			#reset-cells = <1>;

		};



		apmu@e6151000 {

			compatible = "renesas,r8a77470-apmu", "renesas,apmu";

			reg = <0 0xe6151000 0 0x188>;

			cpus = <&cpu0 &cpu1>;

		};



		rst: reset-controller@e6160000 {

			compatible = "renesas,r8a77470-rst";

			reg = <0 0xe6160000 0 0x100>;
@@ -221,6 +237,20 @@ 
			reg = <0 0xe6300000 0 0x20000>;

		};



		i2c4: i2c@e6520000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "renesas,i2c-r8a77470",

				     "renesas,rcar-gen2-i2c";

			reg = <0 0xe6520000 0 0x40>;

			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 927>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 927>;

			i2c-scl-internal-delay-ns = <6>;

			status = "disabled";

		};



		dmac0: dma-controller@e6700000 {

			compatible = "renesas,dmac-r8a77470",

				     "renesas,rcar-dmac";
@@ -396,6 +426,21 @@ 
			status = "disabled";

		};



		sdhi2: sd@ee160000 {

			compatible = "renesas,sdhi-r8a77470",

				     "renesas,rcar-gen2-sdhi";

			reg = <0 0xee160000 0 0x328>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,

			       <&dmac1 0xd3>, <&dmac1 0xd4>;

			dma-names = "tx", "rx", "tx", "rx";

			max-frequency = <97500000>;

			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;

			resets = <&cpg 312>;

			status = "disabled";

		};



		gic: interrupt-controller@f1001000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;

arch/arm/boot/dts/r8a7778-bockw.dts

+1 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Reference Device Tree Source for the Bock-W board

 * Reference Device Tree Source for the R-Car M1A (R8A77781) Bock-W board

 *

 * Copyright (C) 2013  Renesas Solutions Corp.

 * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

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