Commit 527d9427 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Delete dead code in powerplay 



As not support per DPM level optimization,
so delete activity_target array.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce91b71c

drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

+0 −4
Original line number Diff line number Diff line
@@ -173,16 +173,12 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr) 
static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)

{

	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);

	uint32_t i;

	struct cgs_system_info sys_info = {0};

	int result;



	cz_hwmgr->gfx_ramp_step = 256*25/100;

	cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */



	for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)

		cz_hwmgr->activity_target[i] = CZ_AT_DFLT;



	cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;

	cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;

	cz_hwmgr->clock_slow_down_freq = 25000;

drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h

+0 −2
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ 
#define CZ_NUM_NBPSTATES               4

#define CZ_NUM_NBPMEMORYCLOCK          2

#define MAX_DISPLAY_CLOCK_LEVEL        8

#define CZ_AT_DFLT                     30

#define CZ_MAX_HARDWARE_POWERLEVELS    8

#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0   0x3FFFC102

#define CZ_MIN_DEEP_SLEEP_SCLK         800
@@ -185,7 +184,6 @@ struct cc6_settings { 
};



struct cz_hwmgr {

	uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS];

	uint32_t dpm_interval;



	uint32_t voltage_drop_threshold;

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h

+1 −1
Original line number Diff line number Diff line
@@ -289,7 +289,7 @@ struct smu7_hwmgr { 
	struct smu7_pcie_perf_range          pcie_lane_power_saving;

	bool                                      use_pcie_performance_levels;

	bool                                      use_pcie_power_saving_levels;

	uint32_t                                  mclk_activity_target;

	uint16_t                                  mclk_activity_target;

	uint16_t                                  sclk_activity_target;

	uint32_t                                  mclk_dpm0_activity_target;

	uint32_t                                  low_sclk_interrupt_threshold;

drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c

+3 −7
Original line number Diff line number Diff line
@@ -492,7 +492,7 @@ static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 
	for (i = 0; i < dpm_table->sclk_table.count; i++) {

		result = ci_populate_single_graphic_level(hwmgr,

				dpm_table->sclk_table.dpm_levels[i].value,

				(uint16_t)smu_data->activity_target[i],

				data->sclk_activity_target,

				&levels[i]);

		if (result)

			return result;
@@ -1231,7 +1231,7 @@ static int ci_populate_single_memory_level( 
	memory_level->VoltageDownH = 0;



	/* Indicates maximum activity level for this performance level.*/

	memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;

	memory_level->ActivityLevel = data->mclk_activity_target;

	memory_level->StutterEnable = 0;

	memory_level->StrobeEnable = 0;

	memory_level->EdcReadEnable = 0;
@@ -1515,7 +1515,7 @@ static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, 
	table->MemoryACPILevel.DownH = 100;

	table->MemoryACPILevel.VoltageDownH = 0;

	/* Indicates maximum activity level for this performance level.*/

	table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);

	table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->mclk_activity_target);



	table->MemoryACPILevel.StutterEnable = 0;

	table->MemoryACPILevel.StrobeEnable = 0;
@@ -2802,7 +2802,6 @@ static int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, 


static int ci_smu_init(struct pp_hwmgr *hwmgr)

{

	int i;

	struct ci_smumgr *ci_priv = NULL;



	ci_priv = kzalloc(sizeof(struct ci_smumgr), GFP_KERNEL);
@@ -2810,9 +2809,6 @@ static int ci_smu_init(struct pp_hwmgr *hwmgr) 
	if (ci_priv == NULL)

		return -ENOMEM;



	for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)

		ci_priv->activity_target[i] = 30;



	hwmgr->smu_backend = ci_priv;



	return 0;

drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h

+0 −2
Original line number Diff line number Diff line
@@ -70,8 +70,6 @@ struct ci_smumgr { 
	const struct ci_pt_defaults  *power_tune_defaults;

	SMU7_Discrete_MCRegisters      mc_regs;

	struct ci_mc_reg_table mc_reg_table;

	uint32_t        activity_target[SMU7_MAX_LEVELS_GRAPHICS];



};



#endif

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