Commit 5272b7fc authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/switchtec'

  - Support 64-bit addressing for both streaming and coherent DMA (Wesley
    Sheng)

  - Read vep_vector_number with 16-bit, not 32-bit read (Logan Gunthorpe)

  - Add Intercomm Notify and Upstream Error Containment support (Logan
    Gunthorpe)

  - Remove redundant valid PFF number count (Wesley Sheng)

  - Avoid unnecessary CSR read in ISR (Wesley Sheng)

  - Rename Gen3-specific constants (Logan Gunthorpe)

  - Rework infrastructure to support Gen3- and Gen4-specific code (Logan
    Gunthorpe)

  - Add Gen4 system info register support (Logan Gunthorpe)

  - Add Gen4 flash information interface support (Kelvin Cao)

  - Add Gen4 MRPC GAS access permission check (Kelvin Cao)

* pci/switchtec:
  PCI/switchtec: Add Gen4 device IDs
  PCI/switchtec: Add Gen4 MRPC GAS access permission check
  PCI/switchtec: Add Gen4 flash information interface support
  PCI/switchtec: Add Gen4 system info register support
  PCI/switchtec: Separate Gen3 register structures into unions
  PCI/switchtec: Factor out Gen3 ioctl_flash_part_info()
  PCI/switchtec: Add 'generation' variable
  PCI/switchtec: Rename generation-specific constants
  PCI/switchtec: Move check event ID from mask_event() to switchtec_event_isr()
  PCI/switchtec: Remove redundant valid PFF number count
  PCI/switchtec: Add support for Intercomm Notify and Upstream Error Containment
  PCI/switchtec: Fix vep_vector_number ioread width
  PCI/switchtec: Use dma_set_mask_and_coherent()
parents cee538f6 7a30ebb9
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+18 −0
Original line number Diff line number Diff line
@@ -5368,6 +5368,24 @@ SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
SWITCHTEC_QUIRK(0x8574);  /* PFXI 64XG3 */
SWITCHTEC_QUIRK(0x8575);  /* PFXI 80XG3 */
SWITCHTEC_QUIRK(0x8576);  /* PFXI 96XG3 */
SWITCHTEC_QUIRK(0x4000);  /* PFX 100XG4 */
SWITCHTEC_QUIRK(0x4084);  /* PFX 84XG4  */
SWITCHTEC_QUIRK(0x4068);  /* PFX 68XG4  */
SWITCHTEC_QUIRK(0x4052);  /* PFX 52XG4  */
SWITCHTEC_QUIRK(0x4036);  /* PFX 36XG4  */
SWITCHTEC_QUIRK(0x4028);  /* PFX 28XG4  */
SWITCHTEC_QUIRK(0x4100);  /* PSX 100XG4 */
SWITCHTEC_QUIRK(0x4184);  /* PSX 84XG4  */
SWITCHTEC_QUIRK(0x4168);  /* PSX 68XG4  */
SWITCHTEC_QUIRK(0x4152);  /* PSX 52XG4  */
SWITCHTEC_QUIRK(0x4136);  /* PSX 36XG4  */
SWITCHTEC_QUIRK(0x4128);  /* PSX 28XG4  */
SWITCHTEC_QUIRK(0x4200);  /* PAX 100XG4 */
SWITCHTEC_QUIRK(0x4284);  /* PAX 84XG4  */
SWITCHTEC_QUIRK(0x4268);  /* PAX 68XG4  */
SWITCHTEC_QUIRK(0x4252);  /* PAX 52XG4  */
SWITCHTEC_QUIRK(0x4236);  /* PAX 36XG4  */
SWITCHTEC_QUIRK(0x4228);  /* PAX 28XG4  */

/*
 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
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+15 −2
Original line number Diff line number Diff line
@@ -32,7 +32,18 @@
#define SWITCHTEC_IOCTL_PART_VENDOR5	10
#define SWITCHTEC_IOCTL_PART_VENDOR6	11
#define SWITCHTEC_IOCTL_PART_VENDOR7	12
#define SWITCHTEC_IOCTL_NUM_PARTITIONS	13
#define SWITCHTEC_IOCTL_PART_BL2_0	13
#define SWITCHTEC_IOCTL_PART_BL2_1	14
#define SWITCHTEC_IOCTL_PART_MAP_0	15
#define SWITCHTEC_IOCTL_PART_MAP_1	16
#define SWITCHTEC_IOCTL_PART_KEY_0	17
#define SWITCHTEC_IOCTL_PART_KEY_1	18

#define SWITCHTEC_NUM_PARTITIONS_GEN3	13
#define SWITCHTEC_NUM_PARTITIONS_GEN4	19

/* obsolete: for compatibility with old userspace software */
#define SWITCHTEC_IOCTL_NUM_PARTITIONS	SWITCHTEC_NUM_PARTITIONS_GEN3

struct switchtec_ioctl_flash_info {
	__u64 flash_length;
@@ -98,7 +109,9 @@ struct switchtec_ioctl_event_summary {
#define SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT		27
#define SWITCHTEC_IOCTL_EVENT_LINK_STATE		28
#define SWITCHTEC_IOCTL_EVENT_GFMS			29
#define SWITCHTEC_IOCTL_MAX_EVENTS			30
#define SWITCHTEC_IOCTL_EVENT_INTERCOMM_REQ_NOTIFY	30
#define SWITCHTEC_IOCTL_EVENT_UEC			31
#define SWITCHTEC_IOCTL_MAX_EVENTS			32

#define SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX -1
#define SWITCHTEC_IOCTL_EVENT_IDX_ALL -2