Unverified Commit 524353ea authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
Browse files

clk: sunxi-ng: add support for the Allwinner H6 CCU 



The Allwinner H6 SoC has a CCU which has been largely rearranged.

Add support for it in the sunxi-ng CCU framework.

Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 2e08e4d2

drivers/clk/sunxi-ng/Kconfig

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Original line number Diff line number Diff line
@@ -11,6 +11,11 @@ config SUN50I_A64_CCU 
	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN50I_H6_CCU

	bool "Support for the Allwinner H6 CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN4I_A10_CCU

	bool "Support for the Allwinner A10/A20 CCU"

	default MACH_SUN4I

drivers/clk/sunxi-ng/Makefile

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@@ -22,6 +22,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o 


# SoC support

obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o

obj-$(CONFIG_SUN50I_H6_CCU)	+= ccu-sun50i-h6.o

obj-$(CONFIG_SUN4I_A10_CCU)	+= ccu-sun4i-a10.o

obj-$(CONFIG_SUN5I_CCU)		+= ccu-sun5i.o

obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

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+1207 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/sunxi-ng/ccu-sun50i-h6.h

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright 2016 Icenowy Zheng <icenowy@aosc.io>

 */



#ifndef _CCU_SUN50I_H6_H_

#define _CCU_SUN50I_H6_H_



#include <dt-bindings/clock/sun50i-h6-ccu.h>

#include <dt-bindings/reset/sun50i-h6-ccu.h>



#define CLK_OSC12M		0

#define CLK_PLL_CPUX		1

#define CLK_PLL_DDR0		2



/* PLL_PERIPH0 exported for PRCM */



#define CLK_PLL_PERIPH0_2X	4

#define CLK_PLL_PERIPH0_4X	5

#define CLK_PLL_PERIPH1		6

#define CLK_PLL_PERIPH1_2X	7

#define CLK_PLL_PERIPH1_4X	8

#define CLK_PLL_GPU		9

#define CLK_PLL_VIDEO0		10

#define CLK_PLL_VIDEO0_4X	11

#define CLK_PLL_VIDEO1		12

#define CLK_PLL_VIDEO1_4X	13

#define CLK_PLL_VE		14

#define CLK_PLL_DE		15

#define CLK_PLL_HSIC		16

#define CLK_PLL_AUDIO_BASE	17

#define CLK_PLL_AUDIO		18

#define CLK_PLL_AUDIO_2X	19

#define CLK_PLL_AUDIO_4X	20



/* CPUX clock exported for DVFS */



#define CLK_AXI			22

#define CLK_CPUX_APB		23

#define CLK_PSI_AHB1_AHB2	24

#define CLK_AHB3		25



/* APB1 clock exported for PIO */



#define CLK_APB2		27

#define CLK_MBUS		28



/* All module clocks and bus gates are exported except DRAM */



#define CLK_DRAM		52



#define CLK_BUS_DRAM		60



#define CLK_NUMBER		137



#endif /* _CCU_SUN50I_H6_H_ */

include/dt-bindings/clock/sun50i-h6-ccu.h

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)

/*

 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>

 */



#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_

#define _DT_BINDINGS_CLK_SUN50I_H6_H_



#define CLK_PLL_PERIPH0		3



#define CLK_CPUX		21



#define CLK_APB1		26



#define CLK_DE			29

#define CLK_BUS_DE		30

#define CLK_DEINTERLACE		31

#define CLK_BUS_DEINTERLACE	32

#define CLK_GPU			33

#define CLK_BUS_GPU		34

#define CLK_CE			35

#define CLK_BUS_CE		36

#define CLK_VE			37

#define CLK_BUS_VE		38

#define CLK_EMCE		39

#define CLK_BUS_EMCE		40

#define CLK_VP9			41

#define CLK_BUS_VP9		42

#define CLK_BUS_DMA		43

#define CLK_BUS_MSGBOX		44

#define CLK_BUS_SPINLOCK	45

#define CLK_BUS_HSTIMER		46

#define CLK_AVS			47

#define CLK_BUS_DBG		48

#define CLK_BUS_PSI		49

#define CLK_BUS_PWM		50

#define CLK_BUS_IOMMU		51



#define CLK_MBUS_DMA		53

#define CLK_MBUS_VE		54

#define CLK_MBUS_CE		55

#define CLK_MBUS_TS		56

#define CLK_MBUS_NAND		57

#define CLK_MBUS_CSI		58

#define CLK_MBUS_DEINTERLACE	59



#define CLK_NAND0		61

#define CLK_NAND1		62

#define CLK_BUS_NAND		63

#define CLK_MMC0		64

#define CLK_MMC1		65

#define CLK_MMC2		66

#define CLK_BUS_MMC0		67

#define CLK_BUS_MMC1		68

#define CLK_BUS_MMC2		69

#define CLK_BUS_UART0		70

#define CLK_BUS_UART1		71

#define CLK_BUS_UART2		72

#define CLK_BUS_UART3		73

#define CLK_BUS_I2C0		74

#define CLK_BUS_I2C1		75

#define CLK_BUS_I2C2		76

#define CLK_BUS_I2C3		77

#define CLK_BUS_SCR0		78

#define CLK_BUS_SCR1		79

#define CLK_SPI0		80

#define CLK_SPI1		81

#define CLK_BUS_SPI0		82

#define CLK_BUS_SPI1		83

#define CLK_BUS_EMAC		84

#define CLK_TS			85

#define CLK_BUS_TS		86

#define CLK_IR_TX		87

#define CLK_BUS_IR_TX		88

#define CLK_BUS_THS		89

#define CLK_I2S3		90

#define CLK_I2S0		91

#define CLK_I2S1		92

#define CLK_I2S2		93

#define CLK_BUS_I2S0		94

#define CLK_BUS_I2S1		95

#define CLK_BUS_I2S2		96

#define CLK_BUS_I2S3		97

#define CLK_SPDIF		98

#define CLK_BUS_SPDIF		99

#define CLK_DMIC		100

#define CLK_BUS_DMIC		101

#define CLK_AUDIO_HUB		102

#define CLK_BUS_AUDIO_HUB	103

#define CLK_USB_OHCI0		104

#define CLK_USB_PHY0		105

#define CLK_USB_PHY1		106

#define CLK_USB_OHCI3		107

#define CLK_USB_PHY3		108

#define CLK_USB_HSIC_12M	109

#define CLK_USB_HSIC		110

#define CLK_BUS_OHCI0		111

#define CLK_BUS_OHCI3		112

#define CLK_BUS_EHCI0		113

#define CLK_BUS_XHCI		114

#define CLK_BUS_EHCI3		115

#define CLK_BUS_OTG		116

#define CLK_PCIE_REF_100M	117

#define CLK_PCIE_REF		118

#define CLK_PCIE_REF_OUT	119

#define CLK_PCIE_MAXI		120

#define CLK_PCIE_AUX		121

#define CLK_BUS_PCIE		122

#define CLK_HDMI		123

#define CLK_HDMI_CEC		124

#define CLK_BUS_HDMI		125

#define CLK_BUS_TCON_TOP	126

#define CLK_TCON_LCD0		127

#define CLK_BUS_TCON_LCD0	128

#define CLK_TCON_TV0		129

#define CLK_BUS_TCON_TV0	130

#define CLK_CSI_CCI		131

#define CLK_CSI_TOP		132

#define CLK_CSI_MCLK		133

#define CLK_BUS_CSI		134

#define CLK_HDCP		135

#define CLK_BUS_HDCP		136



#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */

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