Commit 51e3a64f authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915/dg1: Add fake PCH 



DG1 has the south engine display on the same PCI device. Ideally we
could use HAS_PCH_SPLIT(), but that macro is misused all across the
code base to rather signify a range of gens. So add a fake one for DG1
to be used where needed.

Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200713182321.12390-6-lucas.demarchi@intel.com
parent f619e516

drivers/gpu/drm/i915/intel_pch.c

+6 −0
Original line number Diff line number Diff line
@@ -188,6 +188,12 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) 
{

	struct pci_dev *pch = NULL;



	/* DG1 has south engine display on the same PCI device */

	if (IS_DG1(dev_priv)) {

		dev_priv->pch_type = PCH_DG1;

		return;

	}



	/*

	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to

	 * make graphics device passthrough work easy for VMM, that only

drivers/gpu/drm/i915/intel_pch.h

+4 −0
Original line number Diff line number Diff line
@@ -26,6 +26,9 @@ enum intel_pch { 
	PCH_JSP,	/* Jasper Lake PCH */

	PCH_MCC,        /* Mule Creek Canyon PCH */

	PCH_TGP,	/* Tiger Lake PCH */



	/* Fake PCHs, functionality handled on the same PCI dev */

	PCH_DG1 = 1024,

};



#define INTEL_PCH_DEVICE_ID_MASK		0xff80
@@ -56,6 +59,7 @@ enum intel_pch { 


#define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)

#define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)

#define HAS_PCH_DG1(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG1)

#define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)

#define HAS_PCH_MCC(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MCC)

#define HAS_PCH_TGP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_TGP)

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