Commit 51d623b6 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Drop address size from ppgtt_type 



With the introduction of the separate addressable bits into the device
info, we can remove the conflation of the ppgtt size from the ppgtt
type.

Based on a patch by Bob Paauwe.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190314223839.28258-3-chris@chris-wilson.co.uk
parent cbecbcca

drivers/gpu/drm/i915/i915_drv.c

+1 −1
Original line number Diff line number Diff line
@@ -348,7 +348,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, 
		value = HAS_WT(dev_priv);

		break;

	case I915_PARAM_HAS_ALIASING_PPGTT:

		value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);

		value = INTEL_PPGTT(dev_priv);

		break;

	case I915_PARAM_HAS_SEMAPHORES:

		value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);

drivers/gpu/drm/i915/i915_drv.h

+0 −2
Original line number Diff line number Diff line
@@ -2457,8 +2457,6 @@ static inline unsigned int i915_sg_segment_size(void) 
	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)

#define HAS_FULL_PPGTT(dev_priv) \

	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)

#define HAS_FULL_48BIT_PPGTT(dev_priv)	\

	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)



#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \

	GEM_BUG_ON((sizes) == 0); \

drivers/gpu/drm/i915/i915_pci.c

+2 −2
Original line number Diff line number Diff line
@@ -498,7 +498,7 @@ static const struct intel_device_info intel_haswell_gt3_info = { 
	.page_sizes = I915_GTT_PAGE_SIZE_4K | \

		      I915_GTT_PAGE_SIZE_2M, \

	.has_logical_ring_contexts = 1, \

	.ppgtt_type = INTEL_PPGTT_FULL_4LVL, \

	.ppgtt_type = INTEL_PPGTT_FULL, \

	.ppgtt_size = 48, \

	.has_64bit_reloc = 1, \

	.has_reset_engine = 1
@@ -621,7 +621,7 @@ static const struct intel_device_info intel_skylake_gt4_info = { 
	.has_logical_ring_contexts = 1, \

	.has_logical_ring_preemption = 1, \

	.has_guc = 1, \

	.ppgtt_type = INTEL_PPGTT_FULL_4LVL, \

	.ppgtt_type = INTEL_PPGTT_FULL, \

	.ppgtt_size = 48, \

	.has_reset_engine = 1, \

	.has_snoop = true, \

drivers/gpu/drm/i915/intel_device_info.h

+0 −1
Original line number Diff line number Diff line
@@ -80,7 +80,6 @@ enum intel_ppgtt_type { 
	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,

	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,

	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,

	INTEL_PPGTT_FULL_4LVL,

};



#define DEV_INFO_FOR_EACH_FLAG(func) \

drivers/gpu/drm/i915/selftests/huge_pages.c

+1 −1
Original line number Diff line number Diff line
@@ -1709,7 +1709,7 @@ int i915_gem_huge_page_mock_selftests(void) 
		return -ENOMEM;



	/* Pretend to be a device which supports the 48b PPGTT */

	mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL_4LVL;

	mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;

	mkwrite_device_info(dev_priv)->ppgtt_size = 48;



	mutex_lock(&dev_priv->drm.struct_mutex);

CRA Git | Maintained and supported by SUSTech CRA and CCSE