Commit 51bc620b authored by Mao Han's avatar Mao Han Committed by Paul Walmsley
Browse files

riscv: Add support for libdw 



This patch adds support for DWARF register mappings and libdw registers
initialization, which is used by perf callchain analyzing when
--call-graph=dwarf is given.

Signed-off-by: default avatarMao Han <han_mao@c-sky.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Greentime Hu <green.hu@gmail.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: linux-riscv <linux-riscv@lists.infradead.org>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Guo Ren <guoren@kernel.org>
Tested-by: default avatarGreentime Hu <greentime.hu@sifive.com>
Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
parent 98a93b0b

tools/arch/riscv/include/uapi/asm/perf_regs.h

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+42 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */

/* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */



#ifndef _ASM_RISCV_PERF_REGS_H

#define _ASM_RISCV_PERF_REGS_H



enum perf_event_riscv_regs {

	PERF_REG_RISCV_PC,

	PERF_REG_RISCV_RA,

	PERF_REG_RISCV_SP,

	PERF_REG_RISCV_GP,

	PERF_REG_RISCV_TP,

	PERF_REG_RISCV_T0,

	PERF_REG_RISCV_T1,

	PERF_REG_RISCV_T2,

	PERF_REG_RISCV_S0,

	PERF_REG_RISCV_S1,

	PERF_REG_RISCV_A0,

	PERF_REG_RISCV_A1,

	PERF_REG_RISCV_A2,

	PERF_REG_RISCV_A3,

	PERF_REG_RISCV_A4,

	PERF_REG_RISCV_A5,

	PERF_REG_RISCV_A6,

	PERF_REG_RISCV_A7,

	PERF_REG_RISCV_S2,

	PERF_REG_RISCV_S3,

	PERF_REG_RISCV_S4,

	PERF_REG_RISCV_S5,

	PERF_REG_RISCV_S6,

	PERF_REG_RISCV_S7,

	PERF_REG_RISCV_S8,

	PERF_REG_RISCV_S9,

	PERF_REG_RISCV_S10,

	PERF_REG_RISCV_S11,

	PERF_REG_RISCV_T3,

	PERF_REG_RISCV_T4,

	PERF_REG_RISCV_T5,

	PERF_REG_RISCV_T6,

	PERF_REG_RISCV_MAX,

};

#endif /* _ASM_RISCV_PERF_REGS_H */

tools/perf/Makefile.config

+5 −1
Original line number Diff line number Diff line
@@ -60,6 +60,10 @@ ifeq ($(SRCARCH),arm64) 
  LIBUNWIND_LIBS = -lunwind -lunwind-aarch64

endif



ifeq ($(SRCARCH),riscv)

  NO_PERF_REGS := 0

endif



ifeq ($(SRCARCH),csky)

  NO_PERF_REGS := 0

endif
@@ -82,7 +86,7 @@ endif 
# Disable it on all other architectures in case libdw unwind

# support is detected in system. Add supported architectures

# to the check.

ifneq ($(SRCARCH),$(filter $(SRCARCH),x86 arm arm64 powerpc s390 csky))

ifneq ($(SRCARCH),$(filter $(SRCARCH),x86 arm arm64 powerpc s390 csky riscv))

  NO_LIBDW_DWARF_UNWIND := 1

endif

tools/perf/arch/riscv/Build

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+1 −0
Original line number Diff line number Diff line 
perf-y += util/

tools/perf/arch/riscv/Makefile

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ifndef NO_DWARF

PERF_HAVE_DWARF_REGS := 1

endif

PERF_HAVE_ARCH_REGS_QUERY_REGISTER_OFFSET := 1

tools/perf/arch/riscv/include/perf_regs.h

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+96 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */



#ifndef ARCH_PERF_REGS_H

#define ARCH_PERF_REGS_H



#include <stdlib.h>

#include <linux/types.h>

#include <asm/perf_regs.h>



#define PERF_REGS_MASK	((1ULL << PERF_REG_RISCV_MAX) - 1)

#define PERF_REGS_MAX	PERF_REG_RISCV_MAX

#if __riscv_xlen == 64

#define PERF_SAMPLE_REGS_ABI    PERF_SAMPLE_REGS_ABI_64

#else

#define PERF_SAMPLE_REGS_ABI	PERF_SAMPLE_REGS_ABI_32

#endif



#define PERF_REG_IP	PERF_REG_RISCV_PC

#define PERF_REG_SP	PERF_REG_RISCV_SP



static inline const char *perf_reg_name(int id)

{

	switch (id) {

	case PERF_REG_RISCV_PC:

		return "pc";

	case PERF_REG_RISCV_RA:

		return "ra";

	case PERF_REG_RISCV_SP:

		return "sp";

	case PERF_REG_RISCV_GP:

		return "gp";

	case PERF_REG_RISCV_TP:

		return "tp";

	case PERF_REG_RISCV_T0:

		return "t0";

	case PERF_REG_RISCV_T1:

		return "t1";

	case PERF_REG_RISCV_T2:

		return "t2";

	case PERF_REG_RISCV_S0:

		return "s0";

	case PERF_REG_RISCV_S1:

		return "s1";

	case PERF_REG_RISCV_A0:

		return "a0";

	case PERF_REG_RISCV_A1:

		return "a1";

	case PERF_REG_RISCV_A2:

		return "a2";

	case PERF_REG_RISCV_A3:

		return "a3";

	case PERF_REG_RISCV_A4:

		return "a4";

	case PERF_REG_RISCV_A5:

		return "a5";

	case PERF_REG_RISCV_A6:

		return "a6";

	case PERF_REG_RISCV_A7:

		return "a7";

	case PERF_REG_RISCV_S2:

		return "s2";

	case PERF_REG_RISCV_S3:

		return "s3";

	case PERF_REG_RISCV_S4:

		return "s4";

	case PERF_REG_RISCV_S5:

		return "s5";

	case PERF_REG_RISCV_S6:

		return "s6";

	case PERF_REG_RISCV_S7:

		return "s7";

	case PERF_REG_RISCV_S8:

		return "s8";

	case PERF_REG_RISCV_S9:

		return "s9";

	case PERF_REG_RISCV_S10:

		return "s10";

	case PERF_REG_RISCV_S11:

		return "s11";

	case PERF_REG_RISCV_T3:

		return "t3";

	case PERF_REG_RISCV_T4:

		return "t4";

	case PERF_REG_RISCV_T5:

		return "t5";

	case PERF_REG_RISCV_T6:

		return "t6";

	default:

		return NULL;

	}



	return NULL;

}



#endif /* ARCH_PERF_REGS_H */

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