dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding (51b6fe7e) · Commits · 戴 / test

Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in the MMCBUS registers. There is no public documentation on this, but the GPL u-boot sources from the Amlogic BSP show that: - it uses the same XTAL input as the main clock controller - it contains a PLL which seems to be implemented just like the other PLLs in this SoC - there is a power-of-two PLL post-divider Add the documentation and header file for this DDR clock controller. Reviewed-by:

Rob Herring <robh@kernel.org> Acked-by:

Stephen Boyd <sboyd@kernel.org> Signed-off-by:

Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:

Jerome Brunet <jbrunet@baylibre.com>

Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Amlogic DDR Clock Controller Device Tree Bindings

		maintainers:
		- Martin Blumenstingl <martin.blumenstingl@googlemail.com>

		properties:
		compatible:
		enum:
		- amlogic,meson8-ddr-clkc
		- amlogic,meson8b-ddr-clkc

		reg:
		maxItems: 1

		clocks:
		maxItems: 1

		clock-names:
		items:
		- const: xtal

		"#clock-cells":
		const: 1

		required:
		- compatible
		- reg
		- clocks
		- clock-names
		- "#clock-cells"

		additionalProperties: false

		examples:
		- \|
		ddr_clkc: clock-controller@400 {
		compatible = "amlogic,meson8-ddr-clkc";
		reg = <0x400 0x20>;
		clocks = <&xtal>;
		clock-names = "xtal";
		#clock-cells = <1>;
		};

		...

include/dt-bindings/clock/meson8-ddr-clkc.h

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		/* SPDX-License-Identifier: GPL-2.0 */

		#define DDR_CLKID_DDR_PLL_DCO 0
		#define DDR_CLKID_DDR_PLL 1

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