Commit 519ab8b2 authored by Tero Kristo's avatar Tero Kristo Committed by Mike Turquette
Browse files

ARM: OMAP2+: clock: use driver API instead of direct memory read/write 



Clock nodes shall use the services provided by underlying drivers to access
the hardware registers instead of direct memory read/write. Thus, change
all the code to use the new omap2_clk_readl / omap2_clk_writel APIs for this.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 3ada6b10

arch/arm/mach-omap2/clkt_clksel.c

+5 −5
Original line number Diff line number Diff line
@@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) 
{

	u32 v;



	v = __raw_readl(clk->clksel_reg);

	v = omap2_clk_readl(clk, clk->clksel_reg);

	v &= ~clk->clksel_mask;

	v |= field_val << __ffs(clk->clksel_mask);

	__raw_writel(v, clk->clksel_reg);

	omap2_clk_writel(v, clk, clk->clksel_reg);



	v = __raw_readl(clk->clksel_reg); /* OCP barrier */

	v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */

}



/**
@@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk) 
	if (!clk->clksel || !clk->clksel_mask)

		return 0;



	v = __raw_readl(clk->clksel_reg);

	v = omap2_clk_readl(clk, clk->clksel_reg);

	v &= clk->clksel_mask;

	v >>= __ffs(clk->clksel_mask);
@@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) 
	WARN((!clk->clksel || !clk->clksel_mask),

	     "clock: %s: attempt to call on a non-clksel clock", clk_name);



	r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;

	r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask;

	r >>= __ffs(clk->clksel_mask);



	for (clks = clk->clksel; clks->parent && !found; clks++) {

arch/arm/mach-omap2/clkt_dpll.c

+3 −3
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) 
	if (!dd)

		return -EINVAL;



	v = __raw_readl(dd->control_reg);

	v = omap2_clk_readl(clk, dd->control_reg);

	v &= dd->enable_mask;

	v >>= __ffs(dd->enable_mask);
@@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) 
		return 0;



	/* Return bypass rate if DPLL is bypassed */

	v = __raw_readl(dd->control_reg);

	v = omap2_clk_readl(clk, dd->control_reg);

	v &= dd->enable_mask;

	v >>= __ffs(dd->enable_mask);
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) 
			return __clk_get_rate(dd->clk_bypass);

	}



	v = __raw_readl(dd->mult_div1_reg);

	v = omap2_clk_readl(clk, dd->mult_div1_reg);

	dpll_mult = v & dd->mult_mask;

	dpll_mult >>= __ffs(dd->mult_mask);

	dpll_div = v & dd->div1_mask;

arch/arm/mach-omap2/clkt_iclk.c

+12 −8
Original line number Diff line number Diff line
@@ -25,25 +25,29 @@ 
/* XXX */

void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)

{

	u32 v, r;

	u32 v;

	void __iomem *r;



	r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));

	r = (__force void __iomem *)

		((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));



	v = __raw_readl((__force void __iomem *)r);

	v = omap2_clk_readl(clk, r);

	v |= (1 << clk->enable_bit);

	__raw_writel(v, (__force void __iomem *)r);

	omap2_clk_writel(v, clk, r);

}



/* XXX */

void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)

{

	u32 v, r;

	u32 v;

	void __iomem *r;



	r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));

	r = (__force void __iomem *)

		((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));



	v = __raw_readl((__force void __iomem *)r);

	v = omap2_clk_readl(clk, r);

	v &= ~(1 << clk->enable_bit);

	__raw_writel(v, (__force void __iomem *)r);

	omap2_clk_writel(v, clk, r);

}



/* Public data */

arch/arm/mach-omap2/clock.c

+13 −12
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, 


/**

 * _wait_idlest_generic - wait for a module to leave the idle state

 * @clk: module clock to wait for (needed for register offsets)

 * @reg: virtual address of module IDLEST register

 * @mask: value to mask against to determine if the module is active

 * @idlest: idle state indicator (0 or 1) for the clock
@@ -122,14 +123,14 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, 
 * elapsed.  XXX Deprecated - should be moved into drivers for the

 * individual IP block that the IDLEST register exists in.

 */

static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,

				const char *name)

static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,

				u32 mask, u8 idlest, const char *name)

{

	int i = 0, ena = 0;



	ena = (idlest) ? 0 : mask;



	omap_test_timeout(((__raw_readl(reg) & mask) == ena),

	omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena),

			  MAX_MODULE_ENABLE_WAIT, i);



	if (i < MAX_MODULE_ENABLE_WAIT)
@@ -162,7 +163,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 
	/* Not all modules have multiple clocks that their IDLEST depends on */

	if (clk->ops->find_companion) {

		clk->ops->find_companion(clk, &companion_reg, &other_bit);

		if (!(__raw_readl(companion_reg) & (1 << other_bit)))

		if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit)))

			return;

	}
@@ -170,8 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 
	r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);

	if (r) {

		/* IDLEST register not in the CM module */

		_wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,

				     __clk_get_name(clk->hw.clk));

		_wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),

				     idlest_val, __clk_get_name(clk->hw.clk));

	} else {

		cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);

	};
@@ -333,13 +334,13 @@ int omap2_dflt_clk_enable(struct clk_hw *hw) 
	}



	/* FIXME should not have INVERT_ENABLE bit here */

	v = __raw_readl(clk->enable_reg);

	v = omap2_clk_readl(clk, clk->enable_reg);

	if (clk->flags & INVERT_ENABLE)

		v &= ~(1 << clk->enable_bit);

	else

		v |= (1 << clk->enable_bit);

	__raw_writel(v, clk->enable_reg);

	v = __raw_readl(clk->enable_reg); /* OCP barrier */

	omap2_clk_writel(v, clk, clk->enable_reg);

	v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */



	if (clk->ops && clk->ops->find_idlest)

		_omap2_module_wait_ready(clk);
@@ -377,12 +378,12 @@ void omap2_dflt_clk_disable(struct clk_hw *hw) 
		return;

	}



	v = __raw_readl(clk->enable_reg);

	v = omap2_clk_readl(clk, clk->enable_reg);

	if (clk->flags & INVERT_ENABLE)

		v |= (1 << clk->enable_bit);

	else

		v &= ~(1 << clk->enable_bit);

	__raw_writel(v, clk->enable_reg);

	omap2_clk_writel(v, clk, clk->enable_reg);

	/* No OCP barrier needed here since it is a disable operation */



	if (clkdm_control && clk->clkdm)
@@ -478,7 +479,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw) 
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

	u32 v;



	v = __raw_readl(clk->enable_reg);

	v = omap2_clk_readl(clk, clk->enable_reg);



	if (clk->flags & INVERT_ENABLE)

		v ^= BIT(clk->enable_bit);

arch/arm/mach-omap2/clock36xx.c

+4 −3
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) 
	struct clk_divider *parent;

	struct clk_hw *parent_hw;

	u32 dummy_v, orig_v;

	struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk);

	int ret;



	/* Clear PWRDN bit of HSDIVIDER */
@@ -53,15 +54,15 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) 


	/* Restore the dividers */

	if (!ret) {

		orig_v = __raw_readl(parent->reg);

		orig_v = omap2_clk_readl(omap_clk, parent->reg);

		dummy_v = orig_v;



		/* Write any other value different from the Read value */

		dummy_v ^= (1 << parent->shift);

		__raw_writel(dummy_v, parent->reg);

		omap2_clk_writel(dummy_v, omap_clk, parent->reg);



		/* Write the original divider */

		__raw_writel(orig_v, parent->reg);

		omap2_clk_writel(orig_v, omap_clk, parent->reg);

	}



	return ret;

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