Commit 5183a617 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-platform-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 platform updates from Ingo Molnar:
 "The biggest change is the removal of SGI UV1 support, which allowed
  the removal of the legacy EFI old_mmap code as well.

  This removes quite a bunch of old code & quirks"

* tag 'x86-platform-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/efi: Remove unused EFI_UV1_MEMMAP code
  x86/platform/uv: Remove uv bios and efi code related to EFI_UV1_MEMMAP
  x86/efi: Remove references to no-longer-used efi_have_uv1_memmap()
  x86/efi: Delete SGI UV1 detection.
  x86/platform/uv: Remove efi=old_map command line option
  x86/platform/uv: Remove vestigial mention of UV1 platform from bios header
  x86/platform/uv: Remove support for UV1 platform from uv
  x86/platform/uv: Remove support for uv1 platform from uv_hub
  x86/platform/uv: Remove support for UV1 platform from uv_bau
  x86/platform/uv: Remove support for UV1 platform from uv_mmrs
  x86/platform/uv: Remove support for UV1 platform from x2apic_uv_x
  x86/platform/uv: Remove support for UV1 platform from uv_tlb
  x86/platform/uv: Remove support for UV1 platform from uv_time
parents e96ec8cf 3bcf25a4

arch/x86/include/asm/efi.h

+2 −18
Original line number Diff line number Diff line
@@ -22,17 +22,7 @@ extern unsigned long efi_fw_vendor, efi_config_table; 
 *

 * This is the main reason why we're doing stable VA mappings for RT

 * services.

 *

 * SGI UV1 machines are known to be incompatible with this scheme, so we

 * provide an opt-out for these machines via a DMI quirk that sets the

 * attribute below.

 */

#define EFI_UV1_MEMMAP         EFI_ARCH_1



static inline bool efi_have_uv1_memmap(void)

{

	return IS_ENABLED(CONFIG_X86_UV) && efi_enabled(EFI_UV1_MEMMAP);

}



#define EFI32_LOADER_SIGNATURE	"EL32"

#define EFI64_LOADER_SIGNATURE	"EL64"
@@ -122,8 +112,6 @@ struct efi_scratch { 
	efi_sync_low_kernel_mappings();					\

	kernel_fpu_begin();						\

	firmware_restrict_branch_speculation_start();			\

									\

	if (!efi_have_uv1_memmap())					\

	efi_switch_mm(&efi_mm);						\

})
@@ -132,9 +120,7 @@ struct efi_scratch { 


#define arch_efi_call_virt_teardown()					\

({									\

	if (!efi_have_uv1_memmap())					\

	efi_switch_mm(efi_scratch.prev_mm);				\

									\

	firmware_restrict_branch_speculation_end();			\

	kernel_fpu_end();						\

})
@@ -176,8 +162,6 @@ extern void efi_delete_dummy_variable(void); 
extern void efi_switch_mm(struct mm_struct *mm);

extern void efi_recover_from_page_fault(unsigned long phys_addr);

extern void efi_free_boot_services(void);

extern pgd_t * __init efi_uv1_memmap_phys_prolog(void);

extern void __init efi_uv1_memmap_phys_epilog(pgd_t *save_pgd);



/* kexec external ABI */

struct efi_setup_data {

arch/x86/include/asm/uv/bios.h

+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ struct uv_gam_range_entry { 
};



#define	UV_SYSTAB_SIG			"UVST"

#define	UV_SYSTAB_VERSION_1		1	/* UV1/2/3 BIOS version */

#define	UV_SYSTAB_VERSION_1		1	/* UV2/3 BIOS version */

#define	UV_SYSTAB_VERSION_UV4		0x400	/* UV4 BIOS base version */

#define	UV_SYSTAB_VERSION_UV4_1		0x401	/* + gpa_shift */

#define	UV_SYSTAB_VERSION_UV4_2		0x402	/* + TYPE_NVRAM/WINDOW/MBOX */

arch/x86/include/asm/uv/uv.h

+1 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 


#include <asm/tlbflush.h>



enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};

enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC};



struct cpumask;

struct mm_struct;

arch/x86/include/asm/uv/uv_bau.h

+7 −111
Original line number Diff line number Diff line
@@ -46,10 +46,7 @@ 
#define UV_ACT_STATUS_SIZE		2

#define UV_DISTRIBUTION_SIZE		256

#define UV_SW_ACK_NPENDING		8

#define UV1_NET_ENDPOINT_INTD		0x38

#define UV2_NET_ENDPOINT_INTD		0x28

#define UV_NET_ENDPOINT_INTD		(is_uv1_hub() ?			\

			UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)

#define UV_NET_ENDPOINT_INTD		0x28

#define UV_PAYLOADQ_GNODE_SHIFT		49

#define UV_PTC_BASENAME			"sgi_uv/ptc_statistics"

#define UV_BAU_BASENAME			"sgi_uv/bau_tunables"
@@ -64,14 +61,9 @@ 
 * UV2: Bit 19 selects between

 *  (0): 10 microsecond timebase and

 *  (1): 80 microseconds

 *  we're using 560us, similar to UV1: 65 units of 10us

 *  we're using 560us

 */

#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)

#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)



#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD	(is_uv1_hub() ?			\

		UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD :			\

		UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)

#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD	(15UL)

/* assuming UV3 is the same */



#define BAU_MISC_CONTROL_MULT_MASK	3
@@ -148,7 +140,6 @@ 


#define UV_LB_SUBNODEID			0x10



/* these two are the same for UV1 and UV2: */

#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT

#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK

/* 4 bits of software ack period */
@@ -189,8 +180,7 @@ 
#define BAU_DESC_QUALIFIER		0x534749



enum uv_bau_version {

	UV_BAU_V1 = 1,

	UV_BAU_V2,

	UV_BAU_V2 = 2,

	UV_BAU_V3,

	UV_BAU_V4,

};
@@ -233,12 +223,12 @@ struct bau_local_cpumask { 
 */



/**

 * struct uv1_2_3_bau_msg_payload - defines payload for INTD transactions

 * struct uv2_3_bau_msg_payload - defines payload for INTD transactions

 * @address:		Signifies a page or all TLB's of the cpu

 * @sending_cpu:	CPU from which the message originates

 * @acknowledge_count:	CPUs on the destination Hub that received the interrupt

 */

struct uv1_2_3_bau_msg_payload {

struct uv2_3_bau_msg_payload {

	u64 address;

	u16 sending_cpu;

	u16 acknowledge_count;
@@ -259,89 +249,6 @@ struct uv4_bau_msg_payload { 
	u32 qualifier:24;

};



/*

 * UV1 Message header:  16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)

 * see table 4.2.3.0.1 in broacast_assist spec.

 */

struct uv1_bau_msg_header {

	unsigned int	dest_subnodeid:6;	/* must be 0x10, for the LB */

	/* bits 5:0 */

	unsigned int	base_dest_nasid:15;	/* nasid of the first bit */

	/* bits 20:6 */				/* in uvhub map */

	unsigned int	command:8;		/* message type */

	/* bits 28:21 */

	/* 0x38: SN3net EndPoint Message */

	unsigned int	rsvd_1:3;		/* must be zero */

	/* bits 31:29 */

	/* int will align on 32 bits */

	unsigned int	rsvd_2:9;		/* must be zero */

	/* bits 40:32 */

	/* Suppl_A is 56-41 */

	unsigned int	sequence:16;		/* message sequence number */

	/* bits 56:41 */			/* becomes bytes 16-17 of msg */

						/* Address field (96:57) is

						   never used as an address

						   (these are address bits

						   42:3) */



	unsigned int	rsvd_3:1;		/* must be zero */

	/* bit 57 */

	/* address bits 27:4 are payload */

	/* these next 24  (58-81) bits become bytes 12-14 of msg */

	/* bits 65:58 land in byte 12 */

	unsigned int	replied_to:1;		/* sent as 0 by the source to

						   byte 12 */

	/* bit 58 */

	unsigned int	msg_type:3;		/* software type of the

						   message */

	/* bits 61:59 */

	unsigned int	canceled:1;		/* message canceled, resource

						   is to be freed*/

	/* bit 62 */

	unsigned int	payload_1a:1;		/* not currently used */

	/* bit 63 */

	unsigned int	payload_1b:2;		/* not currently used */

	/* bits 65:64 */



	/* bits 73:66 land in byte 13 */

	unsigned int	payload_1ca:6;		/* not currently used */

	/* bits 71:66 */

	unsigned int	payload_1c:2;		/* not currently used */

	/* bits 73:72 */



	/* bits 81:74 land in byte 14 */

	unsigned int	payload_1d:6;		/* not currently used */

	/* bits 79:74 */

	unsigned int	payload_1e:2;		/* not currently used */

	/* bits 81:80 */



	unsigned int	rsvd_4:7;		/* must be zero */

	/* bits 88:82 */

	unsigned int	swack_flag:1;		/* software acknowledge flag */

	/* bit 89 */

						/* INTD trasactions at

						   destination are to wait for

						   software acknowledge */

	unsigned int	rsvd_5:6;		/* must be zero */

	/* bits 95:90 */

	unsigned int	rsvd_6:5;		/* must be zero */

	/* bits 100:96 */

	unsigned int	int_both:1;		/* if 1, interrupt both sockets

						   on the uvhub */

	/* bit 101*/

	unsigned int	fairness:3;		/* usually zero */

	/* bits 104:102 */

	unsigned int	multilevel:1;		/* multi-level multicast

						   format */

	/* bit 105 */

	/* 0 for TLB: endpoint multi-unicast messages */

	unsigned int	chaining:1;		/* next descriptor is part of

						   this activation*/

	/* bit 106 */

	unsigned int	rsvd_7:21;		/* must be zero */

	/* bits 127:107 */

};



/*

 * UV2 Message header:  16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)

 * see figure 9-2 of harp_sys.pdf
@@ -418,25 +325,14 @@ struct bau_desc { 
	 * message template, consisting of header and payload:

	 */

	union bau_msg_header {

		struct uv1_bau_msg_header	uv1_hdr;

		struct uv2_3_bau_msg_header	uv2_3_hdr;

	} header;



	union bau_payload_header {

		struct uv1_2_3_bau_msg_payload	uv1_2_3;

		struct uv2_3_bau_msg_payload	uv2_3;

		struct uv4_bau_msg_payload	uv4;

	} payload;

};

/* UV1:

 *   -payload--    ---------header------

 *   bytes 0-11    bits 41-56  bits 58-81

 *       A           B  (2)      C (3)

 *

 *            A/B/C are moved to:

 *       A            C          B

 *   bytes 0-11  bytes 12-14  bytes 16-17  (byte 15 filled in by hw as vector)

 *   ------------payload queue-----------

 */

/* UV2:

 *   -payload--    ---------header------

 *   bytes 0-11    bits 70-78  bits 21-44

arch/x86/include/asm/uv/uv_hub.h

+3 −31
Original line number Diff line number Diff line
@@ -224,17 +224,11 @@ static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) 
 * This is a software convention - NOT the hardware revision numbers in

 * the hub chip.

 */

#define UV1_HUB_REVISION_BASE		1

#define UV2_HUB_REVISION_BASE		3

#define UV3_HUB_REVISION_BASE		5

#define UV4_HUB_REVISION_BASE		7

#define UV4A_HUB_REVISION_BASE		8	/* UV4 (fixed) rev 2 */



static inline int is_uv1_hub(void)

{

	return is_uv_hubbed(uv(1));

}



static inline int is_uv2_hub(void)

{

	return is_uv_hubbed(uv(2));
@@ -265,7 +259,7 @@ static inline int is_uvx_hub(void) 


static inline int is_uv_hub(void)

{

	return is_uv1_hub() || is_uvx_hub();

	return is_uvx_hub();

}



union uvh_apicid {
@@ -292,11 +286,6 @@ union uvh_apicid { 
#define UV_PNODE_TO_GNODE(p)		((p) |uv_hub_info->gnode_extra)

#define UV_PNODE_TO_NASID(p)		(UV_PNODE_TO_GNODE(p) << 1)



#define UV1_LOCAL_MMR_BASE		0xf4000000UL

#define UV1_GLOBAL_MMR32_BASE		0xf8000000UL

#define UV1_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)

#define UV1_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)



#define UV2_LOCAL_MMR_BASE		0xfa000000UL

#define UV2_GLOBAL_MMR32_BASE		0xfc000000UL

#define UV2_LOCAL_MMR_SIZE		(32UL * 1024 * 1024)
@@ -313,25 +302,21 @@ union uvh_apicid { 
#define UV4_GLOBAL_MMR32_SIZE		(16UL * 1024 * 1024)



#define UV_LOCAL_MMR_BASE		(				\

					is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \

					is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \

					is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \

					/*is_uv4_hub*/ UV4_LOCAL_MMR_BASE)



#define UV_GLOBAL_MMR32_BASE		(				\

					is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \

					is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \

					is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \

					/*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE)



#define UV_LOCAL_MMR_SIZE		(				\

					is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \

					is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \

					is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \

					/*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE)



#define UV_GLOBAL_MMR32_SIZE		(				\

					is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \

					is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \

					is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \

					/*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE)
@@ -352,8 +337,6 @@ union uvh_apicid { 
#define UVH_APICID		0x002D0E00L

#define UV_APIC_PNODE_SHIFT	6



#define UV_APICID_HIBIT_MASK	0xffff0000



/* Local Bus from cpu's perspective */

#define LOCAL_BUS_BASE		0x1c00000

#define LOCAL_BUS_SIZE		(4 * 1024 * 1024)
@@ -560,15 +543,6 @@ static inline int uv_apicid_to_pnode(int apicid) 
	return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode;

}



/* Convert an apicid to the socket number on the blade */

static inline int uv_apicid_to_socket(int apicid)

{

	if (is_uv1_hub())

		return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;

	else

		return 0;

}



/*

 * Access global MMRs using the low memory MMR32 space. This region supports

 * faster MMR access but not all MMRs are accessible in this space.
@@ -660,7 +634,7 @@ static inline int uv_cpu_blade_processor_id(int cpu) 
	return uv_cpu_info_per(cpu)->blade_cpu_id;

}



/* Blade number to Node number (UV1..UV4 is 1:1) */

/* Blade number to Node number (UV2..UV4 is 1:1) */

static inline int uv_blade_to_node(int blade)

{

	return blade;
@@ -674,7 +648,7 @@ static inline int uv_numa_blade_id(void) 


/*

 * Convert linux node number to the UV blade number.

 * .. Currently for UV1 thru UV4 the node and the blade are identical.

 * .. Currently for UV2 thru UV4 the node and the blade are identical.

 * .. If this changes then you MUST check references to this function!

 */

static inline int uv_node_to_blade_id(int nid)
@@ -821,8 +795,6 @@ static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 
	}

}



extern unsigned int uv_apicid_hibits;



/*

 * Get the minimum revision number of the hub chips within the partition.

 * (See UVx_HUB_REVISION_BASE above for specific values.)

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