drm/amd/display: Adding NV14 IP Parameters

	.xfc_fill_constant_bytes = 0,

};

struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {

	.odm_capable = 1,

	.gpuvm_enable = 0,

	.hostvm_enable = 0,

	.gpuvm_max_page_table_levels = 4,

	.hostvm_max_page_table_levels = 4,

	.hostvm_cached_page_table_levels = 0,

	.num_dsc = 5,

	.rob_buffer_size_kbytes = 168,

	.det_buffer_size_kbytes = 164,

	.dpte_buffer_size_in_pte_reqs_luma = 84,

	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo

	.dpp_output_buffer_pixels = 2560,

	.opp_output_buffer_lines = 1,

	.pixel_chunk_size_kbytes = 8,

	.pte_enable = 1,

	.max_page_table_levels = 4,

	.pte_chunk_size_kbytes = 2,

	.meta_chunk_size_kbytes = 2,

	.writeback_chunk_size_kbytes = 2,

	.line_buffer_size_bits = 789504,

	.is_line_buffer_bpp_fixed = 0,

	.line_buffer_fixed_bpp = 0,

	.dcc_supported = true,

	.max_line_buffer_lines = 12,

	.writeback_luma_buffer_size_kbytes = 12,

	.writeback_chroma_buffer_size_kbytes = 8,

	.writeback_chroma_line_buffer_width_pixels = 4,

	.writeback_max_hscl_ratio = 1,

	.writeback_max_vscl_ratio = 1,

	.writeback_min_hscl_ratio = 1,

	.writeback_min_vscl_ratio = 1,

	.writeback_max_hscl_taps = 12,

	.writeback_max_vscl_taps = 12,

	.writeback_line_buffer_luma_buffer_size = 0,

	.writeback_line_buffer_chroma_buffer_size = 14643,

	.cursor_buffer_size = 8,

	.cursor_chunk_size = 2,

	.max_num_otg = 5,

	.max_num_dpp = 5,

	.max_num_wb = 1,

	.max_dchub_pscl_bw_pix_per_clk = 4,

	.max_pscl_lb_bw_pix_per_clk = 2,

	.max_lb_vscl_bw_pix_per_clk = 4,

	.max_vscl_hscl_bw_pix_per_clk = 4,

	.max_hscl_ratio = 8,

	.max_vscl_ratio = 8,

	.hscl_mults = 4,

	.vscl_mults = 4,

	.max_hscl_taps = 8,

	.max_vscl_taps = 8,

	.dispclk_ramp_margin_percent = 1,

	.underscan_factor = 1.10,

	.min_vblank_lines = 32, //

	.dppclk_delay_subtotal = 77, //

	.dppclk_delay_scl_lb_only = 16,

	.dppclk_delay_scl = 50,

	.dppclk_delay_cnvc_formatter = 8,

	.dppclk_delay_cnvc_cursor = 6,

	.dispclk_delay_subtotal = 87, //

	.dcfclk_cstate_latency = 10, // SRExitTime

	.max_inter_dcn_tile_repeaters = 8,

	.xfc_supported = true,

	.xfc_fill_bw_overhead_percent = 10.0,

	.xfc_fill_constant_bytes = 0,

	.ptoi_supported = 0

};

struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {

	/* Defaults that get patched on driver load from firmware. */

	.clock_limits = {