ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI master mode (51659ca0) · Commits · 戴 / test

sound/soc/fsl/fsl_sai.c

+29 −0

Original line number	Diff line number	Diff line
		@@ -427,6 +427,35 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,

		val_cr4 \|= FSL_SAI_CR4_FRSZ(channels);

		/*
		* For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
		* generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
		* RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
		* error.
		*/

		if (!sai->is_slave_mode) {
		if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
		regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
		FSL_SAI_CR4_SYWD_MASK \| FSL_SAI_CR4_FRSZ_MASK,
		val_cr4);
		regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
		FSL_SAI_CR5_WNW_MASK \| FSL_SAI_CR5_W0W_MASK \|
		FSL_SAI_CR5_FBT_MASK, val_cr5);
		regmap_write(sai->regmap, FSL_SAI_TMR,
		~0UL - ((1 << channels) - 1));
		} else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
		regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
		FSL_SAI_CR4_SYWD_MASK \| FSL_SAI_CR4_FRSZ_MASK,
		val_cr4);
		regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
		FSL_SAI_CR5_WNW_MASK \| FSL_SAI_CR5_W0W_MASK \|
		FSL_SAI_CR5_FBT_MASK, val_cr5);
		regmap_write(sai->regmap, FSL_SAI_RMR,
		~0UL - ((1 << channels) - 1));
		}
		}

		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
		FSL_SAI_CR4_SYWD_MASK \| FSL_SAI_CR4_FRSZ_MASK,
		val_cr4);