Commit 51644df8 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'for-5.10-clk' of... 

Merge tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes

Pull Tegra clk driver fixes from Thierry Reding:

This is a set of small fixes for the Tegra clock driver.

* tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: Fix missing prototype for tegra210_clk_register_emc()
  clk: tegra: Always program PLL_E when enabled
  clk: tegra: Capitalization fixes
parents e56b4d4c 2f878d04

drivers/clk/tegra/clk-pll.c

+2 −5
Original line number Diff line number Diff line
@@ -1611,9 +1611,6 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	unsigned long flags = 0;

	unsigned long input_rate;



	if (clk_pll_is_enabled(hw))

		return 0;



	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));



	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
@@ -1673,7 +1670,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	pll_writel(val, PLLE_SS_CTRL, pll);

	udelay(1);



	/* Enable hw control of xusb brick pll */

	/* Enable HW control of XUSB brick PLL */

	val = pll_readl_misc(pll);

	val &= ~PLLE_MISC_IDDQ_SW_CTRL;

	pll_writel_misc(val, pll);
@@ -1696,7 +1693,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;

	pll_writel(val, XUSBIO_PLL_CFG0, pll);



	/* Enable hw control of SATA pll */

	/* Enable HW control of SATA PLL */

	val = pll_readl(SATA_PLL_CFG0, pll);

	val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;

	val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;

drivers/clk/tegra/clk-tegra210-emc.c

+2 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
#include <linux/io.h>

#include <linux/slab.h>



#include "clk.h"



#define CLK_SOURCE_EMC 0x19c

#define  CLK_SOURCE_EMC_2X_CLK_SRC GENMASK(31, 29)

#define  CLK_SOURCE_EMC_MC_EMC_SAME_FREQ BIT(16)

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