Commit 51615407 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.10-next-dts64' of... 

Merge tag 'v5.10-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt8173:
- add new power domain controller node

mt8183:
- add new power domain controller
- add display, iommu and dsi nodes

mt8192:
- add basic support, pinctrl, uart, spi, i2c and timer

mt8516:
- add auxadc, efuse and usb nodes

mt8167:
- add basic support for the SoC
- add support for the pumkin board

mt6779:
- add initial support, interrupt controller, clocks, uart

mt7622:
-  PWM node for all available PWM channels

* tag 'v5.10-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (25 commits)
  dts64: mt7622: disable spi1 and uart2 because pins are used by pwm
  dts64: mt7622: enable all pwm for bananapi r64
  arm64: dts: mt8183: Add display nodes for MT8183
  arm64: dts: mt8183: Add iommu and larb nodes
  arm64: dts: mt8183: Add dsi node
  arm64: dts: mt8183: Add pwm and backlight node
  arm64: dts: mediatek: Add mt8183 power domains controller
  arm64: dts: mediatek: Add smi_common node for MT8183
  arm64: dts: mediatek: Add mt8173 power domain controller
  dt-bindings: power: Add MT8192 power domains
  dt-bindings: power: Add MT8183 power domains
  dt-bindings: power: Add bindings for the Mediatek SCPSYS power domains controller
  arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile
  arm64: dts: mediatek: add MT8167 pumpkin board dts
  arm64: dts: mediatek: add dtsi for MT8167
  dt-bindings: arm64: dts: mediatek: Add mt8167-pumpkin board
  arm64: dts: mediatek: mt8516: add efuse node
  arm64: dts: mediatek: align GPIO hog names with dtschema
  arm64: dts: mediatek: mt8516: add usb1 node
  arm64: dts: mediatek: mt8516: rename usb phy
  ...

Link: https://lore.kernel.org/r/72fe1c4f-f27c-c455-dfd9-66bde90bb295@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 1c202d0c 5833bc6c

Documentation/devicetree/bindings/arm/mediatek.yaml

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@@ -84,6 +84,10 @@ properties: 
          - enum:

              - mediatek,mt8135-evbp1

          - const: mediatek,mt8135

      - items:

          - enum:

              - mediatek,mt8167-pumpkin

          - const: mediatek,mt8167

      - description: Google Elm (Acer Chromebook R13)

        items:

          - const: google,elm-rev8

Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt

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@@ -17,6 +17,7 @@ Required properties: 
    - "mediatek,mt7622-auxadc": For MT7622 family of SoCs

    - "mediatek,mt8173-auxadc": For MT8173 family of SoCs

    - "mediatek,mt8183-auxadc", "mediatek,mt8173-auxadc": For MT8183 family of SoCs

    - "mediatek,mt8516-auxadc", "mediatek,mt8173-auxadc": For MT8516 family of SoCs

  - reg: Address range of the AUXADC unit.

  - clocks: Should contain a clock specifier for each entry in clock-names

  - clock-names: Should contain "main".

Documentation/devicetree/bindings/power/mediatek,power-controller.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mediatek Power Domains Controller



maintainers:

  - Weiyi Lu <weiyi.lu@mediatek.com>

  - Matthias Brugger <mbrugger@suse.com>



description: |

  Mediatek processors include support for multiple power domains which can be

  powered up/down by software based on different application scenes to save power.



  IP cores belonging to a power domain should contain a 'power-domains'

  property that is a phandle for SCPSYS node representing the domain.



properties:

  $nodename:

    const: power-controller



  compatible:

    enum:

      - mediatek,mt8173-power-controller

      - mediatek,mt8183-power-controller

      - mediatek,mt8192-power-controller



  '#power-domain-cells':

    const: 1



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



patternProperties:

  "^power-domain@[0-9a-f]+$":

    type: object

    description: |

      Represents the power domains within the power controller node as documented

      in Documentation/devicetree/bindings/power/power-domain.yaml.



    properties:



      '#power-domain-cells':

        description:

          Must be 0 for nodes representing a single PM domain and 1 for nodes

          providing multiple PM domains.



      '#address-cells':

        const: 1



      '#size-cells':

        const: 0



      reg:

        description: |

          Power domain index. Valid values are defined in:

              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.

              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.

              "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.

        maxItems: 1



      clocks:

        description: |

          A number of phandles to clocks that need to be enabled during domain

          power-up sequencing.



      clock-names:

        description: |

          List of names of clocks, in order to match the power-up sequencing

          for each power domain we need to group the clocks by name. BASIC

          clocks need to be enabled before enabling the corresponding power

          domain, and should not have a '-' in their name (i.e mm, mfg, venc).

          SUSBYS clocks need to be enabled before releasing the bus protection,

          and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).



          In order to follow properly the power-up sequencing, the clocks must

          be specified by order, adding first the BASIC clocks followed by the

          SUSBSYS clocks.



      mediatek,infracfg:

        $ref: /schemas/types.yaml#definitions/phandle

        description: phandle to the device containing the INFRACFG register range.



      mediatek,smi:

        $ref: /schemas/types.yaml#definitions/phandle

        description: phandle to the device containing the SMI register range.



    patternProperties:

      "^power-domain@[0-9a-f]+$":

        type: object

        description: |

          Represents a power domain child within a power domain parent node.



        properties:



          '#power-domain-cells':

            description:

              Must be 0 for nodes representing a single PM domain and 1 for nodes

              providing multiple PM domains.



          '#address-cells':

            const: 1



          '#size-cells':

            const: 0



          reg:

            maxItems: 1



          clocks:

            description: |

              A number of phandles to clocks that need to be enabled during domain

              power-up sequencing.



          clock-names:

            description: |

              List of names of clocks, in order to match the power-up sequencing

              for each power domain we need to group the clocks by name. BASIC

              clocks need to be enabled before enabling the corresponding power

              domain, and should not have a '-' in their name (i.e mm, mfg, venc).

              SUSBYS clocks need to be enabled before releasing the bus protection,

              and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).



              In order to follow properly the power-up sequencing, the clocks must

              be specified by order, adding first the BASIC clocks followed by the

              SUSBSYS clocks.



          mediatek,infracfg:

            $ref: /schemas/types.yaml#definitions/phandle

            description: phandle to the device containing the INFRACFG register range.



          mediatek,smi:

            $ref: /schemas/types.yaml#definitions/phandle

            description: phandle to the device containing the SMI register range.



        patternProperties:

          "^power-domain@[0-9a-f]+$":

            type: object

            description: |

              Represents a power domain child within a power domain parent node.



            properties:



              '#power-domain-cells':

                description:

                  Must be 0 for nodes representing a single PM domain and 1 for nodes

                  providing multiple PM domains.



              '#address-cells':

                const: 1



              '#size-cells':

                const: 0



              reg:

                maxItems: 1



              clocks:

                description: |

                  A number of phandles to clocks that need to be enabled during domain

                  power-up sequencing.



              clock-names:

                description: |

                  List of names of clocks, in order to match the power-up sequencing

                  for each power domain we need to group the clocks by name. BASIC

                  clocks need to be enabled before enabling the corresponding power

                  domain, and should not have a '-' in their name (i.e mm, mfg, venc).

                  SUSBYS clocks need to be enabled before releasing the bus protection,

                  and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).



                  In order to follow properly the power-up sequencing, the clocks must

                  be specified by order, adding first the BASIC clocks followed by the

                  SUSBSYS clocks.



              mediatek,infracfg:

                $ref: /schemas/types.yaml#definitions/phandle

                description: phandle to the device containing the INFRACFG register range.



              mediatek,smi:

                $ref: /schemas/types.yaml#definitions/phandle

                description: phandle to the device containing the SMI register range.



            required:

              - reg



            additionalProperties: false



        required:

          - reg



        additionalProperties: false



    required:

      - reg



    additionalProperties: false



required:

  - compatible



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt8173-clk.h>

    #include <dt-bindings/power/mt8173-power.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        scpsys: syscon@10006000 {

            compatible = "syscon", "simple-mfd";

            reg = <0 0x10006000 0 0x1000>;



            spm: power-controller {

                compatible = "mediatek,mt8173-power-controller";

                #address-cells = <1>;

                #size-cells = <0>;

                #power-domain-cells = <1>;



                /* power domains of the SoC */

                power-domain@MT8173_POWER_DOMAIN_VDEC {

                    reg = <MT8173_POWER_DOMAIN_VDEC>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>;

                    clock-names = "mm";

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_VENC {

                    reg = <MT8173_POWER_DOMAIN_VENC>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>,

                             <&topckgen CLK_TOP_VENC_SEL>;

                    clock-names = "mm", "venc";

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_ISP {

                    reg = <MT8173_POWER_DOMAIN_ISP>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>;

                    clock-names = "mm";

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_MM {

                    reg = <MT8173_POWER_DOMAIN_MM>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>;

                    clock-names = "mm";

                    #power-domain-cells = <0>;

                    mediatek,infracfg = <&infracfg>;

                };

                power-domain@MT8173_POWER_DOMAIN_VENC_LT {

                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;

                    clocks = <&topckgen CLK_TOP_MM_SEL>,

                             <&topckgen CLK_TOP_VENC_LT_SEL>;

                    clock-names = "mm", "venclt";

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_AUDIO {

                    reg = <MT8173_POWER_DOMAIN_AUDIO>;

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_USB {

                    reg = <MT8173_POWER_DOMAIN_USB>;

                    #power-domain-cells = <0>;

                };

                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {

                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;

                    clocks = <&clk26m>;

                    clock-names = "mfg";

                    #address-cells = <1>;

                    #size-cells = <0>;

                    #power-domain-cells = <1>;



                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {

                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;

                        #address-cells = <1>;

                        #size-cells = <0>;

                        #power-domain-cells = <1>;



                        power-domain@MT8173_POWER_DOMAIN_MFG {

                            reg = <MT8173_POWER_DOMAIN_MFG>;

                            #power-domain-cells = <0>;

                            mediatek,infracfg = <&infracfg>;

                        };

                    };

                };

            };

        };

    };

arch/arm64/boot/dts/mediatek/Makefile

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# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb

arch/arm64/boot/dts/mediatek/mt6779-evb.dts

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright (c) 2019 MediaTek Inc.

 * Author: Mars.C <mars.cheng@mediatek.com>

 *

 */



/dts-v1/;

#include "mt6779.dtsi"



/ {

	model = "MediaTek MT6779 EVB";

	compatible = "mediatek,mt6779-evb", "mediatek,mt6779";



	aliases {

		serial0 = &uart0;

	};



	memory@40000000 {

		device_type = "memory";

		reg = <0 0x40000000 0 0x1e800000>;

	};



	chosen {

		stdout-path = "serial0:921600n8";

	};

};



&uart0 {

	status = "okay";

};

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