Commit 51496e44 authored Apr 01, 2019 by Martin Blumenstingl Committed by Thierry Reding May 09, 2019

pwm: meson: Consider 128 a valid pre-divider



The pre-divider allows configuring longer PWM periods compared to using
the input clock directly. The pre-divider is 7 bit wide, meaning it's
maximum value is 128 (the register value is off-by-one: 0x7f or 127).

Change the loop to also allow for the maximum possible value to be
considered valid.

Fixes: 211ed630 ("pwm: Add support for Meson PWM Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

parent 9ff06679

drivers/pwm/pwm-meson.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -184,7 +184,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
		do_div(fin_ps, fin_freq);

		/* Calc pre_div with the period */
		for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
		for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
		cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
		fin_ps * (pre_div + 1));
		dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
		@@ -193,7 +193,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
		break;
		}

		if (pre_div == MISC_CLK_DIV_MASK) {
		if (pre_div > MISC_CLK_DIV_MASK) {
		dev_err(meson->chip.dev, "unable to get period pre_div\n");
		return -EINVAL;
		}

Admin message