Commit 5138d5c5 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Sebastian Hesselbarth
Browse files

ARM: dts: berlin: correct BG2Q's SM GPIO location. 



The gpio4 and gpio5 are in 0xf7fc0000 apb which is located in the SM domain.
This patch moves gpio4 and gpio5 to the correct location. This patch also
renames them as the following to match the names we internally used in
marvell:
	gpio4 -> sm_gpio1
	gpio5 -> sm_gpio0
	porte -> portf
	portf -> porte

This also matches what we did for BG2 and BG2CD's SM GPIO.

Cc: stable@vger.kernel.org # 3.16+
Fixes: cedf57fc ("ARM: dts: berlin: add the BG2Q GPIO nodes")
Signed-off-by: default avatarJisheng Zhang <jszhang@marvell.com>
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
parent 5adba7c2

arch/arm/boot/dts/berlin2q.dtsi

+30 −30
Original line number Diff line number Diff line
@@ -349,36 +349,6 @@ 
				interrupt-parent = <&gic>;

				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

			};



			gpio4: gpio@5000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x5000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porte: gpio-port@4 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

				};

			};



			gpio5: gpio@c000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0xc000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portf: gpio-port@5 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

				};

			};

		};



		chip: chip-control@ea0000 {
@@ -467,6 +437,21 @@ 
			ranges = <0 0xfc0000 0x10000>;

			interrupt-parent = <&sic>;



			sm_gpio1: gpio@5000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x5000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portf: gpio-port@5 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

				};

			};



			i2c2: i2c@7000 {

				compatible = "snps,designware-i2c";

				#address-cells = <1>;
@@ -517,6 +502,21 @@ 
				status = "disabled";

			};



			sm_gpio0: gpio@c000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0xc000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porte: gpio-port@4 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

				};

			};



			sysctrl: pin-controller@d000 {

				compatible = "marvell,berlin2q-system-ctrl";

				reg = <0xd000 0x100>;

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