Commit 512eae39 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge tag 'PR_4.7_20160503' of... 

Merge tag 'PR_4.7_20160503' of https://git.kernel.org/pub/scm/linux/kernel/git/mzx/devfreq into pm-devfreq

Pull devfreq material for v4.7 from MyungJoo Ham.

"Updates:

- Passive governor: for SoC subsystems that may either
  have an independent voltage rail or have a parent subsystem
  or collegue subsystem sharing a voltage rail, when there
  is a parent of a collegue that is going to be the owner
  of the voltage rail, the dependent subsystem may use the
  passive governor.

- Consolidated exynos bus/mem-if driver: now we have a single
  driver that supports (almost) all Exynos SoC's bus/mem-if subsystems.

- New devfreq drivers included: Exynos NoC probe"

* tag 'PR_4.7_20160503' of https://git.kernel.org/pub/scm/linux/kernel/git/mzx/devfreq:
  PM / devfreq: style/typo fixes
  PM / devfreq: exynos: Add the detailed correlation for Exynos5422 bus
  PM / devfreq: event: Find the instance of devfreq-event device by using phandle
  PM / devfreq: event: Add new Exynos NoC probe driver
  MAINTAINERS: Add samsung bus frequency driver entry
  PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
  PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
  PM / devfreq: exynos: Update documentation for bus devices using passive governor
  PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
  PM / devfreq: Add new passive governor
  PM / devfreq: Add new DEVFREQ_TRANSITION_NOTIFIER notifier
  PM / devfreq: Add devfreq_get_devfreq_by_phandle()
  PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
  PM / devfreq: exynos: Add generic exynos bus frequency driver
parents 04974df8 83cb0e4d

Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt

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* Samsung Exynos NoC (Network on Chip) Probe device



The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus.

NoC provides the primitive values to get the performance data. The packets

that the Network on Chip (NoC) probes detects are transported over

the network infrastructure to observer units. You can configure probes to

capture packets with header or data on the data request response network,

or as traffic debug or statistic collectors. Exynos542x bus has multiple

NoC probes to provide bandwidth information about behavior of the SoC

that you can use while analyzing system performance.



Required properties:

- compatible: Should be "samsung,exynos5420-nocp"

- reg: physical base address of each NoC Probe and length of memory mapped region.



Optional properties:

- clock-names : the name of clock used by the NoC Probe, "nocp"

- clocks : phandles for clock specified in "clock-names" property



Example : NoC Probe nodes in Device Tree are listed below.



	nocp_mem0_0: nocp@10CA1000 {

		compatible = "samsung,exynos5420-nocp";

		reg = <0x10CA1000 0x200>;

	};

Documentation/devicetree/bindings/devfreq/exynos-bus.txt

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* Generic Exynos Bus frequency device



The Samsung Exynos SoC has many buses for data transfer between DRAM

and sub-blocks in SoC. Most Exynos SoCs share the common architecture

for buses. Generally, each bus of Exynos SoC includes a source clock

and a power line, which are able to change the clock frequency

of the bus in runtime. To monitor the usage of each bus in runtime,

the driver uses the PPMU (Platform Performance Monitoring Unit), which

is able to measure the current load of sub-blocks.



The Exynos SoC includes the various sub-blocks which have the each AXI bus.

The each AXI bus has the owned source clock but, has not the only owned

power line. The power line might be shared among one more sub-blocks.

So, we can divide into two type of device as the role of each sub-block.

There are two type of bus devices as following:

- parent bus device

- passive bus device



Basically, parent and passive bus device share the same power line.

The parent bus device can only change the voltage of shared power line

and the rest bus devices (passive bus device) depend on the decision of

the parent bus device. If there are three blocks which share the VDD_xxx

power line, Only one block should be parent device and then the rest blocks

should depend on the parent device as passive device.



	VDD_xxx |--- A block (parent)

		|--- B block (passive)

		|--- C block (passive)



There are a little different composition among Exynos SoC because each Exynos

SoC has different sub-blocks. Therefore, such difference should be specified

in devicetree file instead of each device driver. In result, this driver

is able to support the bus frequency for all Exynos SoCs.



Required properties for all bus devices:

- compatible: Should be "samsung,exynos-bus".

- clock-names : the name of clock used by the bus, "bus".

- clocks : phandles for clock specified in "clock-names" property.

- operating-points-v2: the OPP table including frequency/voltage information

  to support DVFS (Dynamic Voltage/Frequency Scaling) feature.



Required properties only for parent bus device:

- vdd-supply: the regulator to provide the buses with the voltage.

- devfreq-events: the devfreq-event device to monitor the current utilization

  of buses.



Required properties only for passive bus device:

- devfreq: the parent bus device.



Optional properties only for parent bus device:

- exynos,saturation-ratio: the percentage value which is used to calibrate

			the performance count against total cycle count.

- exynos,voltage-tolerance: the percentage value for bus voltage tolerance

			which is used to calculate the max voltage.



Detailed correlation between sub-blocks and power line according to Exynos SoC:

- In case of Exynos3250, there are two power line as following:

	VDD_MIF |--- DMC



	VDD_INT |--- LEFTBUS (parent device)

		|--- PERIL

		|--- MFC

		|--- G3D

		|--- RIGHTBUS

		|--- PERIR

		|--- FSYS

		|--- LCD0

		|--- PERIR

		|--- ISP

		|--- CAM



- In case of Exynos4210, there is one power line as following:

	VDD_INT |--- DMC (parent device)

		|--- LEFTBUS

		|--- PERIL

		|--- MFC(L)

		|--- G3D

		|--- TV

		|--- LCD0

		|--- RIGHTBUS

		|--- PERIR

		|--- MFC(R)

		|--- CAM

		|--- FSYS

		|--- GPS

		|--- LCD0

		|--- LCD1



- In case of Exynos4x12, there are two power line as following:

	VDD_MIF |--- DMC



	VDD_INT |--- LEFTBUS (parent device)

		|--- PERIL

		|--- MFC(L)

		|--- G3D

		|--- TV

		|--- IMAGE

		|--- RIGHTBUS

		|--- PERIR

		|--- MFC(R)

		|--- CAM

		|--- FSYS

		|--- GPS

		|--- LCD0

		|--- ISP



- In case of Exynos5422, there are two power line as following:

	VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)

	        |--- DREX 1



	VDD_INT |--- NoC_Core (parent device)

		|--- G2D

		|--- G3D

		|--- DISP1

		|--- NoC_WCORE

		|--- GSCL

		|--- MSCL

		|--- ISP

		|--- MFC

		|--- GEN

		|--- PERIS

		|--- PERIC

		|--- FSYS

		|--- FSYS2



Example1:

	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to

	power line (regulator). The MIF (Memory Interface) AXI bus is used to

	transfer data between DRAM and CPU and uses the VDD_MIF regulator.



	- MIF (Memory Interface) block

	: VDD_MIF |--- DMC (Dynamic Memory Controller)



	- INT (Internal) block

	: VDD_INT |--- LEFTBUS (parent device)

		  |--- PERIL

		  |--- MFC

		  |--- G3D

		  |--- RIGHTBUS

		  |--- FSYS

		  |--- LCD0

		  |--- PERIR

		  |--- ISP

		  |--- CAM



	- MIF bus's frequency/voltage table

	-----------------------

	|Lv| Freq   | Voltage |

	-----------------------

	|L1| 50000  |800000   |

	|L2| 100000 |800000   |

	|L3| 134000 |800000   |

	|L4| 200000 |825000   |

	|L5| 400000 |875000   |

	-----------------------



	- INT bus's frequency/voltage table

	----------------------------------------------------------

	|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |

	| name|       |LCD0    |       |       |       ||        |

	|     |       |FSYS    |       |       |       ||        |

	|     |       |MFC     |       |       |       ||        |

	----------------------------------------------------------

	|Mode |*parent|passive |passive|passive|passive||        |

	----------------------------------------------------------

	|Lv   |Frequency                               ||Voltage |

	----------------------------------------------------------

	|L1   |50000  |50000   |50000  |50000  |50000  ||900000  |

	|L2   |80000  |80000   |80000  |80000  |80000  ||900000  |

	|L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |

	|L4   |134000 |134000  |200000 |200000 |       ||1000000 |

	|L5   |200000 |200000  |400000 |300000 |       ||1000000 |

	----------------------------------------------------------



Example2 :

	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi

	is listed below:



	bus_dmc: bus_dmc {

		compatible = "samsung,exynos-bus";

		clocks = <&cmu_dmc CLK_DIV_DMC>;

		clock-names = "bus";

		operating-points-v2 = <&bus_dmc_opp_table>;

		status = "disabled";

	};



	bus_dmc_opp_table: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@50000000 {

			opp-hz = /bits/ 64 <50000000>;

			opp-microvolt = <800000>;

		};

		opp@100000000 {

			opp-hz = /bits/ 64 <100000000>;

			opp-microvolt = <800000>;

		};

		opp@134000000 {

			opp-hz = /bits/ 64 <134000000>;

			opp-microvolt = <800000>;

		};

		opp@200000000 {

			opp-hz = /bits/ 64 <200000000>;

			opp-microvolt = <825000>;

		};

		opp@400000000 {

			opp-hz = /bits/ 64 <400000000>;

			opp-microvolt = <875000>;

		};

	};



	bus_leftbus: bus_leftbus {

		compatible = "samsung,exynos-bus";

		clocks = <&cmu CLK_DIV_GDL>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_rightbus: bus_rightbus {

		compatible = "samsung,exynos-bus";

		clocks = <&cmu CLK_DIV_GDR>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_lcd0: bus_lcd0 {

		compatible = "samsung,exynos-bus";

		clocks = <&cmu CLK_DIV_ACLK_160>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_fsys: bus_fsys {

		compatible = "samsung,exynos-bus";

		clocks = <&cmu CLK_DIV_ACLK_200>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_mcuisp: bus_mcuisp {

		compatible = "samsung,exynos-bus";

		clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;

		clock-names = "bus";

		operating-points-v2 = <&bus_mcuisp_opp_table>;

		status = "disabled";

	};



	bus_isp: bus_isp {

		compatible = "samsung,exynos-bus";

		clocks = <&cmu CLK_DIV_ACLK_266>;

		clock-names = "bus";

		operating-points-v2 = <&bus_isp_opp_table>;

		status = "disabled";

	};



	bus_peril: bus_peril {

		compatible = "samsung,exynos-bus";

		clocks = <&cmu CLK_DIV_ACLK_100>;

		clock-names = "bus";

		operating-points-v2 = <&bus_peril_opp_table>;

		status = "disabled";

	};



	bus_mfc: bus_mfc {

		compatible = "samsung,exynos-bus";

		clocks = <&cmu CLK_SCLK_MFC>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_leftbus_opp_table: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@50000000 {

			opp-hz = /bits/ 64 <50000000>;

			opp-microvolt = <900000>;

		};

		opp@80000000 {

			opp-hz = /bits/ 64 <80000000>;

			opp-microvolt = <900000>;

		};

		opp@100000000 {

			opp-hz = /bits/ 64 <100000000>;

			opp-microvolt = <1000000>;

		};

		opp@134000000 {

			opp-hz = /bits/ 64 <134000000>;

			opp-microvolt = <1000000>;

		};

		opp@200000000 {

			opp-hz = /bits/ 64 <200000000>;

			opp-microvolt = <1000000>;

		};

	};



	bus_mcuisp_opp_table: opp_table2 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@50000000 {

			opp-hz = /bits/ 64 <50000000>;

		};

		opp@80000000 {

			opp-hz = /bits/ 64 <80000000>;

		};

		opp@100000000 {

			opp-hz = /bits/ 64 <100000000>;

		};

		opp@200000000 {

			opp-hz = /bits/ 64 <200000000>;

		};

		opp@400000000 {

			opp-hz = /bits/ 64 <400000000>;

		};

	};



	bus_isp_opp_table: opp_table3 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@50000000 {

			opp-hz = /bits/ 64 <50000000>;

		};

		opp@80000000 {

			opp-hz = /bits/ 64 <80000000>;

		};

		opp@100000000 {

			opp-hz = /bits/ 64 <100000000>;

		};

		opp@200000000 {

			opp-hz = /bits/ 64 <200000000>;

		};

		opp@300000000 {

			opp-hz = /bits/ 64 <300000000>;

		};

	};



	bus_peril_opp_table: opp_table4 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@50000000 {

			opp-hz = /bits/ 64 <50000000>;

		};

		opp@80000000 {

			opp-hz = /bits/ 64 <80000000>;

		};

		opp@100000000 {

			opp-hz = /bits/ 64 <100000000>;

		};

	};





	Usage case to handle the frequency and voltage of bus on runtime

	in exynos3250-rinato.dts is listed below:



	&bus_dmc {

		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;

		vdd-supply = <&buck1_reg>;	/* VDD_MIF */

		status = "okay";

	};



	&bus_leftbus {

		devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;

		vdd-supply = <&buck3_reg>;

		status = "okay";

	};



	&bus_rightbus {

		devfreq = <&bus_leftbus>;

		status = "okay";

	};



	&bus_lcd0 {

		devfreq = <&bus_leftbus>;

		status = "okay";

	};



	&bus_fsys {

		devfreq = <&bus_leftbus>;

		status = "okay";

	};



	&bus_mcuisp {

		devfreq = <&bus_leftbus>;

		status = "okay";

	};



	&bus_isp {

		devfreq = <&bus_leftbus>;

		status = "okay";

	};



	&bus_peril {

		devfreq = <&bus_leftbus>;

		status = "okay";

	};



	&bus_mfc {

		devfreq = <&bus_leftbus>;

		status = "okay";

	};

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -3539,6 +3539,15 @@ F: drivers/devfreq/devfreq-event.c 
F:	include/linux/devfreq-event.h

F:	Documentation/devicetree/bindings/devfreq/event/



BUS FREQUENCY DRIVER FOR SAMSUNG EXYNOS

M:	Chanwoo Choi <cw00.choi@samsung.com>

L:	linux-pm@vger.kernel.org

L:	linux-samsung-soc@vger.kernel.org

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/mzx/devfreq.git

S:	Maintained

F:	drivers/devfreq/exynos-bus.c

F:	Documentation/devicetree/bindings/devfreq/exynos-bus.txt



DEVICE NUMBER REGISTRY

M:	Torben Mathiasen <device@lanana.org>

W:	http://lanana.org/docs/device-list/index.html

drivers/devfreq/Kconfig

+19 −17
Original line number Diff line number Diff line
@@ -64,30 +64,32 @@ config DEVFREQ_GOV_USERSPACE 
	  Otherwise, the governor does not change the frequency

	  given at the initialization.



config DEVFREQ_GOV_PASSIVE

	tristate "Passive"

	help

	  Sets the frequency based on the frequency of its parent devfreq

	  device. This governor does not change the frequency by itself

	  through sysfs entries. The passive governor recommends that

	  devfreq device uses the OPP table to get the frequency/voltage.



comment "DEVFREQ Drivers"



config ARM_EXYNOS4_BUS_DEVFREQ

	bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"

	depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM

config ARM_EXYNOS_BUS_DEVFREQ

	bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"

	depends on ARCH_EXYNOS

	select DEVFREQ_GOV_SIMPLE_ONDEMAND

	select DEVFREQ_GOV_PASSIVE

	select DEVFREQ_EVENT_EXYNOS_PPMU

	select PM_DEVFREQ_EVENT

	select PM_OPP

	help

	  This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)

	  and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).

	  It reads PPMU counters of memory controllers and adjusts

	  the operating frequencies and voltages with OPP support.

	  This adds the common DEVFREQ driver for Exynos Memory bus. Exynos

	  Memory bus has one more group of memory bus (e.g, MIF and INT block).

	  Each memory bus group could contain many memoby bus block. It reads

	  PPMU counters of memory controllers by using DEVFREQ-event device

	  and adjusts the operating frequencies and voltages with OPP support.

	  This does not yet operate with optimal voltages.



config ARM_EXYNOS5_BUS_DEVFREQ

	tristate "ARM Exynos5250 Bus DEVFREQ Driver"

	depends on SOC_EXYNOS5250

	select DEVFREQ_GOV_SIMPLE_ONDEMAND

	select PM_OPP

	help

	  This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int).

	  It reads PPMU counters of memory controllers and adjusts the

	  operating frequencies and voltages with OPP support.



config ARM_TEGRA_DEVFREQ

       tristate "Tegra DEVFREQ Driver"

       depends on ARCH_TEGRA_124_SOC

drivers/devfreq/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -4,10 +4,10 @@ obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) += governor_simpleondemand.o 
obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE)	+= governor_performance.o

obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE)	+= governor_powersave.o

obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)	+= governor_userspace.o

obj-$(CONFIG_DEVFREQ_GOV_PASSIVE)	+= governor_passive.o



# DEVFREQ Drivers

obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)	+= exynos/

obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ)	+= exynos/

obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)	+= exynos-bus.o

obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra-devfreq.o



# DEVFREQ Event Drivers

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