drm/amdgpu: ras support suspend/resume (511fdbc3) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -2745,7 +2745,7 @@ fence_driver_init:
		}

		/* must succeed. */
		amdgpu_ras_post_init(adev);
		amdgpu_ras_resume(adev);

		r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
		if (r) {
		@@ -3503,7 +3503,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
		goto out;

		/* must succeed. */
		amdgpu_ras_post_init(tmp_adev);
		amdgpu_ras_resume(tmp_adev);

		/* Update PSP FW topology after reset */
		if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)

+15 −5

Original line number	Diff line number	Diff line
		@@ -1594,12 +1594,9 @@ recovery_out:
		}

		/* do some init work after IP late init as dependence.
		* TODO
		* gpu reset will re-enable ras, need fint out one way to run it again.
		* for now, if a gpu reset happened, unless IP enable its ras, the ras state
		* will be showed as disabled.
		* and it runs in resume/gpu reset/booting up cases.
		*/
		void amdgpu_ras_post_init(struct amdgpu_device *adev)
		void amdgpu_ras_resume(struct amdgpu_device *adev)
		{
		struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
		struct ras_manager obj, tmp;
		@@ -1642,6 +1639,19 @@ void amdgpu_ras_post_init(struct amdgpu_device *adev)
		}
		}

		void amdgpu_ras_suspend(struct amdgpu_device *adev)
		{
		struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

		if (!con)
		return;

		amdgpu_ras_disable_all_features(adev, 0);
		/* Make sure all ras objects are disabled. */
		if (con->features)
		amdgpu_ras_disable_all_features(adev, 1);
		}

		/* do some fini work before IP fini as dependence */
		int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
		{

+3 −1

Original line number	Diff line number	Diff line
		@@ -179,6 +179,9 @@ static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
		int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
		unsigned int block);

		void amdgpu_ras_resume(struct amdgpu_device *adev);
		void amdgpu_ras_suspend(struct amdgpu_device *adev);

		int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
		bool is_ce);

		@@ -256,7 +259,6 @@ amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {

		/* called in ip_init and ip_fini */
		int amdgpu_ras_init(struct amdgpu_device *adev);
		void amdgpu_ras_post_init(struct amdgpu_device *adev);
		int amdgpu_ras_fini(struct amdgpu_device *adev);
		int amdgpu_ras_pre_fini(struct amdgpu_device *adev);