Merge tag 'tegra-for-5.6-arm-core' of... (511f96fb) · Commits · 戴 / test

arch/arm/mach-tegra/sleep-tegra30.S

+28 −2

Original line number	Diff line number	Diff line
		@@ -59,6 +59,9 @@
		#define CLK_RESET_PLLX_MISC3_IDDQ 3
		#define CLK_RESET_PLLM_MISC_IDDQ 5
		#define CLK_RESET_PLLC_MISC_IDDQ 26
		#define CLK_RESET_PLLP_RESHIFT 0x528
		#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
		#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3

		#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4

		@@ -370,6 +373,18 @@ _pll_m_c_x_done:
		pll_locked r1, r0, CLK_RESET_PLLC_BASE
		pll_locked r1, r0, CLK_RESET_PLLX_BASE

		tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
		cmp r1, #TEGRA30
		beq 1f

		ldr r1, [r0, #CLK_RESET_PLLP_BASE]
		bic r1, r1, #(1<<31) @ disable PllP bypass
		str r1, [r0, #CLK_RESET_PLLP_BASE]

		mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
		str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
		1:

		mov32 r7, TEGRA_TMRUS_BASE
		ldr r1, [r7]
		add r1, r1, #LOCK_DELAY
		@@ -630,9 +645,16 @@ tegra30_switch_cpu_to_clk32k:
		str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]

		/* disable PLLP, PLLA, PLLC and PLLX */
		tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
		cmp r1, #TEGRA30
		ldr r0, [r5, #CLK_RESET_PLLP_BASE]
		orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
		bic r0, r0, #(1 << 30)
		str r0, [r5, #CLK_RESET_PLLP_BASE]
		beq 1f
		mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
		str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
		1:
		ldr r0, [r5, #CLK_RESET_PLLA_BASE]
		bic r0, r0, #(1 << 30)
		str r0, [r5, #CLK_RESET_PLLA_BASE]
		@@ -648,8 +670,12 @@ tegra30_switch_cpu_to_clk32k:
		pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
		_no_pll_in_iddq:

		/* switch to CLKS */
		mov r0, #0 /* brust policy = 32KHz */
		/*
		* Switch to clk_s (32KHz); bits 28:31=0
		* Enable burst on CPU IRQ; bit 24=1
		* Set IRQ burst clock source to clk_m; bits 10:8=0
		*/
		mov r0, #(1 << 24)
		str r0, [r5, #CLK_RESET_SCLK_BURST]

		ret lr

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