Commit 50fb83a6 authored by Dave Hansen's avatar Dave Hansen Committed by Ingo Molnar
Browse files

x86/mm: Move the CR3 construction functions to tlbflush.h 



For flushing the TLB, the ASID which has been programmed into the hardware
must be known.  That differs from what is in 'cpu_tlbstate'.

Add functions to transform the 'cpu_tlbstate' values into to the one
programmed into the hardware (CR3).

It's not easy to include mmu_context.h into tlbflush.h, so just move the
CR3 building over to tlbflush.h.

Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: David Laight <David.Laight@aculab.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Eduardo Valentin <eduval@amazon.com>
Cc: Greg KH <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: aliguori@amazon.com
Cc: daniel.gruss@iaik.tugraz.at
Cc: hughd@google.com
Cc: keescook@google.com
Cc: linux-mm@kvack.org
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 3f67af51

arch/x86/include/asm/mmu_context.h

+1 −28
Original line number Diff line number Diff line
@@ -290,33 +290,6 @@ static inline bool arch_vma_access_permitted(struct vm_area_struct *vma, 
	return __pkru_allows_pkey(vma_pkey(vma), write);

}



/*

 * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID

 * bits.  This serves two purposes.  It prevents a nasty situation in

 * which PCID-unaware code saves CR3, loads some other value (with PCID

 * == 0), and then restores CR3, thus corrupting the TLB for ASID 0 if

 * the saved ASID was nonzero.  It also means that any bugs involving

 * loading a PCID-enabled CR3 with CR4.PCIDE off will trigger

 * deterministically.

 */



static inline unsigned long build_cr3(struct mm_struct *mm, u16 asid)

{

	if (static_cpu_has(X86_FEATURE_PCID)) {

		VM_WARN_ON_ONCE(asid > 4094);

		return __sme_pa(mm->pgd) | (asid + 1);

	} else {

		VM_WARN_ON_ONCE(asid != 0);

		return __sme_pa(mm->pgd);

	}

}



static inline unsigned long build_cr3_noflush(struct mm_struct *mm, u16 asid)

{

	VM_WARN_ON_ONCE(asid > 4094);

	return __sme_pa(mm->pgd) | (asid + 1) | CR3_NOFLUSH;

}



/*

 * This can be used from process context to figure out what the value of

 * CR3 is without needing to do a (slow) __read_cr3().
@@ -326,7 +299,7 @@ static inline unsigned long build_cr3_noflush(struct mm_struct *mm, u16 asid) 
 */

static inline unsigned long __get_current_cr3_fast(void)

{

	unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm),

	unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,

		this_cpu_read(cpu_tlbstate.loaded_mm_asid));



	/* For now, be very restrictive about when this can be called. */

arch/x86/include/asm/tlbflush.h

+26 −0
Original line number Diff line number Diff line
@@ -69,6 +69,32 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) 
	return atomic64_inc_return(&mm->context.tlb_gen);

}



/*

 * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID bits.

 * This serves two purposes.  It prevents a nasty situation in which

 * PCID-unaware code saves CR3, loads some other value (with PCID == 0),

 * and then restores CR3, thus corrupting the TLB for ASID 0 if the saved

 * ASID was nonzero.  It also means that any bugs involving loading a

 * PCID-enabled CR3 with CR4.PCIDE off will trigger deterministically.

 */

struct pgd_t;

static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)

{

	if (static_cpu_has(X86_FEATURE_PCID)) {

		VM_WARN_ON_ONCE(asid > 4094);

		return __sme_pa(pgd) | (asid + 1);

	} else {

		VM_WARN_ON_ONCE(asid != 0);

		return __sme_pa(pgd);

	}

}



static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)

{

	VM_WARN_ON_ONCE(asid > 4094);

	return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;

}



#ifdef CONFIG_PARAVIRT

#include <asm/paravirt.h>

#else

arch/x86/mm/tlb.c

+4 −4
Original line number Diff line number Diff line
@@ -128,7 +128,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, 
	 * isn't free.

	 */

#ifdef CONFIG_DEBUG_VM

	if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev, prev_asid))) {

	if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {

		/*

		 * If we were to BUG here, we'd be very likely to kill

		 * the system so hard that we don't see the call trace.
@@ -195,7 +195,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, 
		if (need_flush) {

			this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);

			this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);

			write_cr3(build_cr3(next, new_asid));

			write_cr3(build_cr3(next->pgd, new_asid));



			/*

			 * NB: This gets called via leave_mm() in the idle path
@@ -208,7 +208,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, 
			trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);

		} else {

			/* The new ASID is already up to date. */

			write_cr3(build_cr3_noflush(next, new_asid));

			write_cr3(build_cr3_noflush(next->pgd, new_asid));



			/* See above wrt _rcuidle. */

			trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0);
@@ -288,7 +288,7 @@ void initialize_tlbstate_and_flush(void) 
		!(cr4_read_shadow() & X86_CR4_PCIDE));



	/* Force ASID 0 and force a TLB flush. */

	write_cr3(build_cr3(mm, 0));

	write_cr3(build_cr3(mm->pgd, 0));



	/* Reinitialize tlbstate. */

	this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);

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