Commit 50f737ab authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.6_v2' of... 

Merge tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into usb-next

Kishon writes:

phy: for 5.6

*) Add support in PHY core to create link between PHY consumer and PHY
   provider
*) Add DisplayPort PHY configuration set to be used for negotiating the
   configurations to be used between DisplayPort controller and
   DisplayPort PHY
*) Add PHY wrapper driver (configure inputs to Cadence Sierra PHY) for
   TI's J721E SoC and adapt Cadence Sierra PHY driver to be used for
   J721E SoC (Supports USB and PCIe)
*) Add PHY driver for eMMC PHY in Intel LGM SoC
*) Add PHY support for 7216 and 7211 Broadcom SoCs which uses the new
   Synopsys USB Controller
*) Add support for 16nm SATA PHY present in Broadcom 7216 SoC
*) Fix lost packet issue, fix MDIO from getting inaccessible, fix
   occasional transaction failures, fix USB driver from crashing in
   Broadcom USB PHY driver
*) Fix missing PCS SW reset in UFS PHY of Qualcomm SM8150
*) Use "struct phy_configure_opts_mipi_dphy" to pass parameters from
   display controller to rockchip-inno-dsidphy
*) Other cleanups including compile testing for some of the PHY drivers,
   fixing Kconfig indentation, duplicate writes in drivers etc.,

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (54 commits)
  dt-bindings: phy: Add PHY_TYPE_DP definition
  phy: ti: j721e-wiz: Fix return value check in wiz_probe()
  dt-bindings: usb: Convert Allwinner A80 USB PHY controller to a schema
  phy: intel-lgm-emmc: Fix warning by adding missing MODULE_LICENSE
  phy: ti: j721e-wiz: Manage typec-gpio-dir
  dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO
  phy: cadence: Sierra: add phy_reset hook
  phy: cadence: Sierra: remove redundant initialization of pointer regmap
  phy: Add DisplayPort configuration options
  phy: Enable compile testing for some of drivers
  phy: mediatek: Fix Kconfig indentation
  phy: intel-lgm-emmc: Add support for eMMC PHY
  dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY
  phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC
  dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
  phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()
  phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
  phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
  phy: cadence: Sierra: Check for PLL lock during PHY power on
  phy: cadence: Sierra: Get reset control "array" for each link
  ...
parents 4baa550e 8a79db5e

Documentation/devicetree/bindings/phy/allwinner,sun9i-a80-usb-phy.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner A80 USB PHY Device Tree Bindings



maintainers:

  - Chen-Yu Tsai <wens@csie.org>

  - Maxime Ripard <mripard@kernel.org>



properties:

  "#phy-cells":

    const: 0



  compatible:

    const: allwinner,sun9i-a80-usb-phy



  reg:

    maxItems: 1



  clocks:

    anyOf:

      - description: Main PHY Clock



      - items:

          - description: Main PHY clock

          - description: HSIC 12MHz clock

          - description: HSIC 480MHz clock



  clock-names:

    oneOf:

      - const: phy



      - items:

          - const: phy

          - const: hsic_12M

          - const: hsic_480M



  resets:

    anyOf:

      - description: Normal USB PHY reset



      - items:

          - description: Normal USB PHY reset

          - description: HSIC Reset



  reset-names:

    oneOf:

      - const: phy



      - items:

          - const: phy

          - const: hsic



  phy_type:

    const: hsic

    description:

      When absent, the PHY type will be assumed to be normal USB.



  phy-supply:

    description:

      Regulator that powers VBUS



required:

  - "#phy-cells"

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - reset-names



additionalProperties: false



if:

  properties:

    phy_type:

      const: hsic



  required:

    - phy_type



then:

  properties:

    clocks:

      maxItems: 3



    clock-names:

      maxItems: 3



    resets:

      maxItems: 2



    reset-names:

      maxItems: 2



examples:

  - |

    #include <dt-bindings/clock/sun9i-a80-usb.h>

    #include <dt-bindings/reset/sun9i-a80-usb.h>



    usbphy1: phy@a00800 {

        compatible = "allwinner,sun9i-a80-usb-phy";

        reg = <0x00a00800 0x4>;

        clocks = <&usb_clocks CLK_USB0_PHY>;

        clock-names = "phy";

        resets = <&usb_clocks RST_USB0_PHY>;

        reset-names = "phy";

        phy-supply = <&reg_usb1_vbus>;

        #phy-cells = <0>;

    };



  - |

    #include <dt-bindings/clock/sun9i-a80-usb.h>

    #include <dt-bindings/reset/sun9i-a80-usb.h>



    usbphy3: phy@a02800 {

        compatible = "allwinner,sun9i-a80-usb-phy";

        reg = <0x00a02800 0x4>;

        clocks = <&usb_clocks CLK_USB2_PHY>,

                 <&usb_clocks CLK_USB_HSIC>,

                 <&usb_clocks CLK_USB2_HSIC>;

        clock-names = "phy",

                      "hsic_12M",

                      "hsic_480M";

        resets = <&usb_clocks RST_USB2_PHY>,

                 <&usb_clocks RST_USB2_HSIC>;

        reset-names = "phy",

                      "hsic";

        phy_type = "hsic";

        phy-supply = <&reg_usb3_vbus>;

        #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt

+56 −13
Original line number Diff line number Diff line 
Broadcom STB USB PHY



Required properties:

 - compatible: brcm,brcmstb-usb-phy

 - reg: two offset and length pairs.

	The first pair specifies a manditory set of memory mapped

	registers used for general control of the PHY.

	The second pair specifies optional registers used by some of

	the SoCs that support USB 3.x

- compatible: should be one of

	"brcm,brcmstb-usb-phy"

	"brcm,bcm7216-usb-phy"

	"brcm,bcm7211-usb-phy"



- reg and reg-names properties requirements are specific to the

  compatible string.

  "brcm,brcmstb-usb-phy":

    - reg: 1 or 2 offset and length pairs. One for the base CTRL registers

           and an optional pair for systems with USB 3.x support

    - reg-names: not specified

  "brcm,bcm7216-usb-phy":

    - reg: 3 offset and length pairs for CTRL, XHCI_EC and XHCI_GBL

           registers

    - reg-names: "ctrl", "xhci_ec", "xhci_gbl"

  "brcm,bcm7211-usb-phy":

    - reg: 5 offset and length pairs for CTRL, XHCI_EC, XHCI_GBL,

           USB_PHY and USB_MDIO registers and an optional pair

	   for the BDC registers

    - reg-names: "ctrl", "xhci_ec", "xhci_gbl", "usb_phy", "usb_mdio", "bdc_ec"



- #phy-cells: Shall be 1 as it expects one argument for setting

	      the type of the PHY. Possible values are:

	      - PHY_TYPE_USB2 for USB1.1/2.0 PHY
@@ -15,16 +30,20 @@ Required properties: 
Optional Properties:

- clocks : clock phandles.

- clock-names: String, clock name.

- interrupts: wakeup interrupt

- interrupt-names: "wakeup"

- brcm,ipp: Boolean, Invert Port Power.

  Possible values are: 0 (Don't invert), 1 (Invert)

- brcm,ioc: Boolean, Invert Over Current detection.

  Possible values are: 0 (Don't invert), 1 (Invert)

NOTE: one or both of the following two properties must be set

- brcm,has-xhci: Boolean indicating the phy has an XHCI phy.

- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy.

- dr_mode: String, PHY Device mode.

  Possible values are: "host", "peripheral ", "drd" or "typec-pd"

  If this property is not defined, the phy will default to "host" mode.

- brcm,syscon-piarbctl: phandle to syscon for handling config registers

NOTE: one or both of the following two properties must be set

- brcm,has-xhci: Boolean indicating the phy has an XHCI phy.

- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy.





Example:
@@ -41,3 +60,27 @@ usbphy_0: usb-phy@f0470200 { 
	clocks = <&usb20>, <&usb30>;

	clock-names = "sw_usb", "sw_usb3";

};



usb-phy@29f0200 {

	reg = <0x29f0200 0x200>,

		<0x29c0880 0x30>,

		<0x29cc100 0x534>,

		<0x2808000 0x24>,

		<0x2980080 0x8>;

	reg-names = "ctrl",

		"xhci_ec",

		"xhci_gbl",

		"usb_phy",

		"usb_mdio";

	brcm,ioc = <0x0>;

	brcm,ipp = <0x0>;

	compatible = "brcm,bcm7211-usb-phy";

	interrupts = <0x30>;

	interrupt-parent = <&vpu_intr1_nosec_intc>;

	interrupt-names = "wake";

	#phy-cells = <0x1>;

	brcm,has-xhci;

	syscon-piarbctl = <&syscon_piarbctl>;

	clocks = <&scmi_clk 256>;

	clock-names = "sw_usb";

};

Documentation/devicetree/bindings/phy/brcm-sata-phy.txt

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@@ -2,6 +2,7 @@ 


Required properties:

- compatible: should be one or more of

     "brcm,bcm7216-sata-phy"

     "brcm,bcm7425-sata-phy"

     "brcm,bcm7445-sata-phy"

     "brcm,iproc-ns2-sata-phy"

Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings



maintainers:

  - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>



description: |+

  Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon

  node is used to reference the base address of eMMC phy registers.



  The eMMC PHY node should be the child of a syscon node with the

  required property:



  - compatible:         Should be one of the following:

                        "intel,lgm-syscon", "syscon"

  - reg:

      maxItems: 1



properties:

  compatible:

      const: intel,lgm-emmc-phy



  "#phy-cells":

    const: 0



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



required:

  - "#phy-cells"

  - compatible

  - reg

  - clocks



examples:

  - |

    sysconf: chiptop@e0200000 {

      compatible = "intel,lgm-syscon", "syscon";

      reg = <0xe0200000 0x100>;



      emmc-phy: emmc-phy@a8 {

        compatible = "intel,lgm-emmc-phy";

        reg = <0x00a8 0x10>;

        clocks = <&emmc>;

        #phy-cells = <0>;

      };

    };

...

Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt

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@@ -2,21 +2,24 @@ Cadence Sierra PHY 
-----------------------



Required properties:

- compatible:	cdns,sierra-phy-t0

- clocks:	Must contain an entry in clock-names.

		See ../clocks/clock-bindings.txt for details.

- clock-names:	Must be "phy_clk"

- compatible:	Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform

		Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.

- resets:	Must contain an entry for each in reset-names.

		See ../reset/reset.txt for details.

- reset-names:	Must include "sierra_reset" and "sierra_apb".

		"sierra_reset" must control the reset line to the PHY.

		"sierra_apb" must control the reset line to the APB PHY

		interface.

		interface ("sierra_apb" is optional).

- reg:		register range for the PHY.

- #address-cells: Must be 1

- #size-cells:	Must be 0



Optional properties:

- clocks:		Must contain an entry in clock-names.

			See ../clocks/clock-bindings.txt for details.

- clock-names:		Must contain "cmn_refclk_dig_div" and

			"cmn_refclk1_dig_div" for configuring the frequency of

			the clock to the lanes. "phy_clk" is deprecated.

- cdns,autoconf:	A boolean property whose presence indicates that the

			PHY registers will be configured by hardware. If not

			present, all sub-node optional properties must be

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