Commit 50cf6707 authored by Dave Jiang's avatar Dave Jiang Committed by Paul Mackerras
Browse files

[POWERPC] 85xx: Add device nodes for error reporting devices used by EDAC 



Adding memory-controller and l2-cache-controller entries to be used by EDAC
as of_devices for MPC8540 ADS, MPC8548 CDS, and MPC8560 ADS.

Also fixed up the size of the PCI node on MPC8560 ADS.

Signed-off-by: default avatarDave Jiang <djiang@mvista.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 1c2de47c

arch/powerpc/boot/dts/mpc8540ads.dts

+16 −0
Original line number Diff line number Diff line
@@ -48,6 +48,22 @@ 
		reg = <e0000000 00100000>;	// CCSRBAR 1M

		bus-frequency = <0>;



		memory-controller@2000 {

			compatible = "fsl,8540-memory-controller";

			reg = <2000 1000>;

			interrupt-parent = <&mpic>;

			interrupts = <2 2>;

		};



		l2-cache-controller@20000 {

			compatible = "fsl,8540-l2-cache-controller";

			reg = <20000 1000>;

			cache-line-size = <20>;	// 32 bytes

			cache-size = <40000>;	// L2, 256K

			interrupt-parent = <&mpic>;

			interrupts = <0 2>;

		};



		i2c@3000 {

			device_type = "i2c";

			compatible = "fsl-i2c";

arch/powerpc/boot/dts/mpc8548cds.dts

+16 −0
Original line number Diff line number Diff line
@@ -48,6 +48,22 @@ 
		reg = <e0000000 00100000>;	// CCSRBAR 1M

		bus-frequency = <0>;



		memory-controller@2000 {

			compatible = "fsl,8548-memory-controller";

			reg = <2000 1000>;

			interrupt-parent = <&mpic>;

			interrupts = <2 2>;

		};



		l2-cache-controller@20000 {

			compatible = "fsl,8548-l2-cache-controller";

			reg = <20000 1000>;

			cache-line-size = <20>;	// 32 bytes

			cache-size = <80000>;	// L2, 512K

			interrupt-parent = <&mpic>;

			interrupts = <0 2>;

		};



		i2c@3000 {

			device_type = "i2c";

			compatible = "fsl-i2c";

arch/powerpc/boot/dts/mpc8560ads.dts

+17 −1
Original line number Diff line number Diff line
@@ -48,6 +48,22 @@ 
		reg = <e0000000 00000200>;

		bus-frequency = <13ab6680>;



		memory-controller@2000 {

			compatible = "fsl,8540-memory-controller";

			reg = <2000 1000>;

			interrupt-parent = <&mpic>;

			interrupts = <2 2>;

		};



		l2-cache-controller@20000 {

			compatible = "fsl,8540-l2-cache-controller";

			reg = <20000 1000>;

			cache-line-size = <20>;	// 32 bytes

			cache-size = <40000>;	// L2, 256K

			interrupt-parent = <&mpic>;

			interrupts = <0 2>;

		};



		mdio@24520 {

			device_type = "mdio";

			compatible = "gianfar";
@@ -110,7 +126,7 @@ 
			#address-cells = <3>;

			compatible = "85xx";

			device_type = "pci";

			reg = <8000 400>;

			reg = <8000 1000>;

			clock-frequency = <3f940aa>;

			interrupt-map-mask = <f800 0 0 7>;

			interrupt-map = <

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