Commit 50b6f619 authored by Mika Kahola's avatar Mika Kahola Committed by Daniel Vetter
Browse files

uapi/drm/drm_fourcc.h: Note on platform specificity for format modifiers 



Make an additional note on DRM format modifiers for x and y tiling. These
format modifiers are defined for BDW+ platforms and therefore definition
is not valid for older gens. This is due to address swizzling for tiled
surfaces is no longer used. For newer platforms main memory controller has
a more effective address swizzling algorithm.

v2: Rephrase comment (Daniel)

Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20200506120827.12250-1-mika.kahola@intel.com
parent d6ddbd5c

include/uapi/drm/drm_fourcc.h

+12 −6
Original line number Diff line number Diff line
@@ -354,9 +354,12 @@ extern "C" { 
 * a platform-dependent stride. On top of that the memory can apply

 * platform-depending swizzling of some higher address bits into bit6.

 *

 * This format is highly platforms specific and not useful for cross-driver

 * sharing. It exists since on a given platform it does uniquely identify the

 * layout in a simple way for i915-specific userspace.

 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.

 * On earlier platforms the is highly platforms specific and not useful for

 * cross-driver sharing. It exists since on a given platform it does uniquely

 * identify the layout in a simple way for i915-specific userspace, which

 * facilitated conversion of userspace to modifiers. Additionally the exact

 * format on some really old platforms is not known.

 */

#define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 1)
@@ -369,9 +372,12 @@ extern "C" { 
 * memory can apply platform-depending swizzling of some higher address bits

 * into bit6.

 *

 * This format is highly platforms specific and not useful for cross-driver

 * sharing. It exists since on a given platform it does uniquely identify the

 * layout in a simple way for i915-specific userspace.

 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.

 * On earlier platforms the is highly platforms specific and not useful for

 * cross-driver sharing. It exists since on a given platform it does uniquely

 * identify the layout in a simple way for i915-specific userspace, which

 * facilitated conversion of userspace to modifiers. Additionally the exact

 * format on some really old platforms is not known.

 */

#define I915_FORMAT_MOD_Y_TILED	fourcc_mod_code(INTEL, 2)

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