Commit 509efa2b authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Return the mask of enabled infoframes from ->inforame_enabled() 



We want to start tracking which infoframes are enabled, so let's replace
the boolean flag with a bitmask.

We'll abstract the bitmask so that it's not platform dependent. That
will allow us to examine the bitmask later in platform independent code.

v2: Don't map VIDEO_DIP_ENABLE to the null packet (Daniel)
    Put a FIXME in the lspcon function

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20190225174106.2163-3-ville.syrjala@linux.intel.com
parent 5cb3c1a1

drivers/gpu/drm/i915/intel_ddi.c

+1 −1
Original line number Diff line number Diff line
@@ -3764,7 +3764,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, 
		pipe_config->has_hdmi_sink = true;

		intel_dig_port = enc_to_dig_port(&encoder->base);



		if (intel_dig_port->infoframe_enabled(encoder, pipe_config))

		if (intel_hdmi_infoframes_enabled(encoder, pipe_config))

			pipe_config->has_infoframe = true;



		if (temp & TRANS_DDI_HDMI_SCRAMBLING)

drivers/gpu/drm/i915/intel_drv.h

+4 −2
Original line number Diff line number Diff line
@@ -1349,7 +1349,7 @@ struct intel_digital_port { 
			       bool enable,

			       const struct intel_crtc_state *crtc_state,

			       const struct drm_connector_state *conn_state);

	bool (*infoframe_enabled)(struct intel_encoder *encoder,

	u32 (*infoframes_enabled)(struct intel_encoder *encoder,

				  const struct intel_crtc_state *pipe_config);

};
@@ -2084,6 +2084,8 @@ bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 
				       bool scrambling);

void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);

void intel_infoframe_init(struct intel_digital_port *intel_dig_port);

u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,

				  const struct intel_crtc_state *crtc_state);



/* intel_lvds.c */

bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
@@ -2501,7 +2503,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, 
			   bool enable,

			   const struct intel_crtc_state *crtc_state,

			   const struct drm_connector_state *conn_state);

bool lspcon_infoframe_enabled(struct intel_encoder *encoder,

u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,

			      const struct intel_crtc_state *pipe_config);

void lspcon_ycbcr420_config(struct drm_connector *connector,

			    struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/intel_hdmi.c

+58 −25
Original line number Diff line number Diff line
@@ -103,6 +103,8 @@ static u32 g4x_infoframe_enable(unsigned int type) 
		return VIDEO_DIP_ENABLE_GCP;

	case HDMI_PACKET_TYPE_GAMUT_METADATA:

		return VIDEO_DIP_ENABLE_GAMUT;

	case DP_SDP_VSC:

		return 0;

	case HDMI_INFOFRAME_TYPE_AVI:

		return VIDEO_DIP_ENABLE_AVI;

	case HDMI_INFOFRAME_TYPE_SPD:
@@ -212,17 +214,17 @@ static void g4x_write_infoframe(struct intel_encoder *encoder, 
	POSTING_READ(VIDEO_DIP_CTL);

}



static bool g4x_infoframe_enabled(struct intel_encoder *encoder,

static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,

				  const struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 val = I915_READ(VIDEO_DIP_CTL);



	if ((val & VIDEO_DIP_ENABLE) == 0)

		return false;

		return 0;



	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))

		return false;

		return 0;



	return val & (VIDEO_DIP_ENABLE_AVI |

		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
@@ -267,7 +269,7 @@ static void ibx_write_infoframe(struct intel_encoder *encoder, 
	POSTING_READ(reg);

}



static bool ibx_infoframe_enabled(struct intel_encoder *encoder,

static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,

				  const struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -276,10 +278,10 @@ static bool ibx_infoframe_enabled(struct intel_encoder *encoder, 
	u32 val = I915_READ(reg);



	if ((val & VIDEO_DIP_ENABLE) == 0)

		return false;

		return 0;



	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))

		return false;

		return 0;



	return val & (VIDEO_DIP_ENABLE_AVI |

		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
@@ -328,7 +330,7 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, 
	POSTING_READ(reg);

}



static bool cpt_infoframe_enabled(struct intel_encoder *encoder,

static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,

				  const struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -336,7 +338,7 @@ static bool cpt_infoframe_enabled(struct intel_encoder *encoder, 
	u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));



	if ((val & VIDEO_DIP_ENABLE) == 0)

		return false;

		return 0;



	return val & (VIDEO_DIP_ENABLE_AVI |

		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
@@ -382,7 +384,7 @@ static void vlv_write_infoframe(struct intel_encoder *encoder, 
	POSTING_READ(reg);

}



static bool vlv_infoframe_enabled(struct intel_encoder *encoder,

static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,

				  const struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -390,10 +392,10 @@ static bool vlv_infoframe_enabled(struct intel_encoder *encoder, 
	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));



	if ((val & VIDEO_DIP_ENABLE) == 0)

		return false;

		return 0;



	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))

		return false;

		return 0;



	return val & (VIDEO_DIP_ENABLE_AVI |

		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
@@ -435,7 +437,7 @@ static void hsw_write_infoframe(struct intel_encoder *encoder, 
	POSTING_READ(ctl_reg);

}



static bool hsw_infoframe_enabled(struct intel_encoder *encoder,

static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,

				  const struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -446,6 +448,41 @@ static bool hsw_infoframe_enabled(struct intel_encoder *encoder, 
		      VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);

}



static const u8 infoframe_type_to_idx[] = {

	HDMI_PACKET_TYPE_GENERAL_CONTROL,

	HDMI_PACKET_TYPE_GAMUT_METADATA,

	DP_SDP_VSC,

	HDMI_INFOFRAME_TYPE_AVI,

	HDMI_INFOFRAME_TYPE_SPD,

	HDMI_INFOFRAME_TYPE_VENDOR,

};



u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,

				  const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);

	u32 val, ret = 0;

	int i;



	val = dig_port->infoframes_enabled(encoder, crtc_state);



	/* map from hardware bits to dip idx */

	for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {

		unsigned int type = infoframe_type_to_idx[i];



		if (HAS_DDI(dev_priv)) {

			if (val & hsw_infoframe_enable(type))

				ret |= BIT(i);

		} else {

			if (val & g4x_infoframe_enable(type))

				ret |= BIT(i);

		}

	}



	return ret;

}



/*

 * The data we write to the DIP data buffer registers is 1 byte bigger than the

 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
@@ -1448,7 +1485,6 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, 
				  struct intel_crtc_state *pipe_config)

{

	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);

	struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	u32 tmp, flags = 0;
@@ -1471,7 +1507,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, 
	if (tmp & HDMI_MODE_SELECT_HDMI)

		pipe_config->has_hdmi_sink = true;



	if (intel_dig_port->infoframe_enabled(encoder, pipe_config))

	if (intel_hdmi_infoframes_enabled(encoder, pipe_config))

		pipe_config->has_infoframe = true;



	if (tmp & SDVO_AUDIO_ENABLE)
@@ -2599,32 +2635,29 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port) 
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		intel_dig_port->write_infoframe = vlv_write_infoframe;

		intel_dig_port->set_infoframes = vlv_set_infoframes;

		intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;

		intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;

	} else if (IS_G4X(dev_priv)) {

		intel_dig_port->write_infoframe = g4x_write_infoframe;

		intel_dig_port->set_infoframes = g4x_set_infoframes;

		intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;

		intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;

	} else if (HAS_DDI(dev_priv)) {

		if (intel_dig_port->lspcon.active) {

			intel_dig_port->write_infoframe =

					lspcon_write_infoframe;

			intel_dig_port->write_infoframe = lspcon_write_infoframe;

			intel_dig_port->set_infoframes = lspcon_set_infoframes;

			intel_dig_port->infoframe_enabled =

						lspcon_infoframe_enabled;

			intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;

		} else {

			intel_dig_port->set_infoframes = hsw_set_infoframes;

			intel_dig_port->infoframe_enabled =

						hsw_infoframe_enabled;

			intel_dig_port->write_infoframe = hsw_write_infoframe;

			intel_dig_port->set_infoframes = hsw_set_infoframes;

			intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;

		}

	} else if (HAS_PCH_IBX(dev_priv)) {

		intel_dig_port->write_infoframe = ibx_write_infoframe;

		intel_dig_port->set_infoframes = ibx_set_infoframes;

		intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;

		intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;

	} else {

		intel_dig_port->write_infoframe = cpt_write_infoframe;

		intel_dig_port->set_infoframes = cpt_set_infoframes;

		intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;

		intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;

	}

}

drivers/gpu/drm/i915/intel_lspcon.c

+2 −1
Original line number Diff line number Diff line
@@ -504,9 +504,10 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, 
				  buf, ret);

}



bool lspcon_infoframe_enabled(struct intel_encoder *encoder,

u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,

			      const struct intel_crtc_state *pipe_config)

{

	/* FIXME actually read this from the hw */

	return enc_to_intel_lspcon(&encoder->base)->active;

}

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