Commit 505caa66 authored by Christian Daudt's avatar Christian Daudt Committed by Russell King
Browse files

ARM: 7821/1: DT: binding fixup to align with vendor-prefixes.txt 

[ this is a follow-up to this discussion:
http://archive.arm.linux.org.uk/lurker/message/20130730.230827.a1ceb12a.en.html

 ]
This patchset renames all uses of "bcm," name bindings to
"brcm," as they were done prior to knowing that brcm had
already been standardized as Broadcom vendor prefix
(in Documentation/devicetree/bindings/vendor-prefixes.txt).
This will not cause any churn on devices because none of
these bindings have made it into production yet.

Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarChristian Daudt <csd@broadcom.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent c477b8db

Documentation/devicetree/bindings/arm/l2cc.txt

+3 −1
Original line number Original line Diff line number Diff line
@@ -16,9 +16,11 @@ Required properties: 
     performs the same operation).

     performs the same operation).

	"marvell,"aurora-outer-cache: Marvell Controller designed to be

	"marvell,"aurora-outer-cache: Marvell Controller designed to be

	 compatible with the ARM one with outer cache mode.

	 compatible with the ARM one with outer cache mode.

	"bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an

	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an

	offset needs to be added to the address before passing down to the L2

	offset needs to be added to the address before passing down to the L2

	cache controller

	cache controller

	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by

	                               "brcm,bcm11351-a2-pl310-cache"

- cache-unified : Specifies the cache is a unified cache.

- cache-unified : Specifies the cache is a unified cache.

- cache-level : Should be set to 2 for a level 2 cache.

- cache-level : Should be set to 2 for a level 2 cache.

- reg : Physical base address and size of cache controller's memory mapped

- reg : Physical base address and size of cache controller's memory mapped

arch/arm/mm/cache-l2x0.c

+3 −1
Original line number Original line Diff line number Diff line
@@ -929,7 +929,9 @@ static const struct of_device_id l2x0_ids[] __initconst = { 
	  .data = (void *)&aurora_no_outer_data},

	  .data = (void *)&aurora_no_outer_data},

	{ .compatible = "marvell,aurora-outer-cache",

	{ .compatible = "marvell,aurora-outer-cache",

	  .data = (void *)&aurora_with_outer_data},

	  .data = (void *)&aurora_with_outer_data},

	{ .compatible = "bcm,bcm11351-a2-pl310-cache",

	{ .compatible = "brcm,bcm11351-a2-pl310-cache",

	  .data = (void *)&bcm_l2x0_data},

	{ .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */

	  .data = (void *)&bcm_l2x0_data},

	  .data = (void *)&bcm_l2x0_data},

	{}

	{}

};

};

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