Commit 504792e0 authored by Jerin Jacob's avatar Jerin Jacob Committed by Daniel Borkmann
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arm64: bpf: optimize modulo operation 



Optimize modulo operation instruction generation by
using single MSUB instruction vs MUL followed by SUB
instruction scheme.

Signed-off-by: default avatarJerin Jacob <jerinj@marvell.com>
Signed-off-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
parent 53092f7e

arch/arm64/net/bpf_jit.h

+3 −0
Original line number Diff line number Diff line
@@ -171,6 +171,9 @@ 
/* Rd = Ra + Rn * Rm */

#define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \

	A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD)

/* Rd = Ra - Rn * Rm */

#define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \

	A64_VARIANT(sf), AARCH64_INSN_DATA3_MSUB)

/* Rd = Rn * Rm */

#define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)

arch/arm64/net/bpf_jit_comp.c

+2 −4
Original line number Diff line number Diff line
@@ -409,8 +409,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, 
			break;

		case BPF_MOD:

			emit(A64_UDIV(is64, tmp, dst, src), ctx);

			emit(A64_MUL(is64, tmp, tmp, src), ctx);

			emit(A64_SUB(is64, dst, dst, tmp), ctx);

			emit(A64_MSUB(is64, dst, dst, tmp, src), ctx);

			break;

		}

		break;
@@ -516,8 +515,7 @@ emit_bswap_uxt: 
	case BPF_ALU64 | BPF_MOD | BPF_K:

		emit_a64_mov_i(is64, tmp2, imm, ctx);

		emit(A64_UDIV(is64, tmp, dst, tmp2), ctx);

		emit(A64_MUL(is64, tmp, tmp, tmp2), ctx);

		emit(A64_SUB(is64, dst, dst, tmp), ctx);

		emit(A64_MSUB(is64, dst, dst, tmp, tmp2), ctx);

		break;

	case BPF_ALU | BPF_LSH | BPF_K:

	case BPF_ALU64 | BPF_LSH | BPF_K:

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