Commit 50261151 authored by Nils Wallménius's avatar Nils Wallménius Committed by Alex Deucher
Browse files

drm/amdgpu: simplify allocation of scratch regs 



The scratch regs are sequential so there's no need to keep
them in an array, we can just return the index of the first
free register + the base register. Also change the array
of bools for keeping track of the free regs to a bitfield.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarNils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cb341a31

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −2
Original line number Diff line number Diff line
@@ -794,8 +794,7 @@ struct amdgpu_kiq { 
struct amdgpu_scratch {

	unsigned		num_reg;

	uint32_t                reg_base;

	bool			free[32];

	uint32_t		reg[32];

	uint32_t		free_mask;

};



/*

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+7 −14
Original line number Diff line number Diff line
@@ -42,13 +42,13 @@ int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg) 
{

	int i;



	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {

		if (adev->gfx.scratch.free[i]) {

			adev->gfx.scratch.free[i] = false;

			*reg = adev->gfx.scratch.reg[i];

	i = ffs(adev->gfx.scratch.free_mask);

	if (i != 0 && i <= adev->gfx.scratch.num_reg) {

		i--;

		adev->gfx.scratch.free_mask &= ~(1u << i);

		*reg = adev->gfx.scratch.reg_base + i;

		return 0;

	}

	}

	return -EINVAL;

}
@@ -62,14 +62,7 @@ int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg) 
 */

void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)

{

	int i;



	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {

		if (adev->gfx.scratch.reg[i] == reg) {

			adev->gfx.scratch.free[i] = true;

			return;

		}

	}

	adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);

}



/**

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+1 −6
Original line number Diff line number Diff line
@@ -1794,14 +1794,9 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) 


static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)

{

	int i;



	adev->gfx.scratch.num_reg = 7;

	adev->gfx.scratch.reg_base = mmSCRATCH_REG0;

	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {

		adev->gfx.scratch.free[i] = true;

		adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;

	}

	adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;

}



static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+1 −6
Original line number Diff line number Diff line
@@ -2003,14 +2003,9 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) 
 */

static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)

{

	int i;



	adev->gfx.scratch.num_reg = 7;

	adev->gfx.scratch.reg_base = mmSCRATCH_REG0;

	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {

		adev->gfx.scratch.free[i] = true;

		adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;

	}

	adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;

}



/**

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+1 −6
Original line number Diff line number Diff line
@@ -749,14 +749,9 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) 


static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)

{

	int i;



	adev->gfx.scratch.num_reg = 7;

	adev->gfx.scratch.reg_base = mmSCRATCH_REG0;

	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {

		adev->gfx.scratch.free[i] = true;

		adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;

	}

	adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;

}



static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)

CRA Git | Maintained and supported by SUSTech CRA and CCSE