Commit 501faf71 authored by Kalle Valo's avatar Kalle Valo
Browse files
ath.git patches for 5.1. Major changes:

ath10k

* more preparation for SDIO support

wil6210

* support up to 20 stations in AP mode
parents 037e0c5d de77a53c
Loading
Loading
Loading
Loading
+64 −2
Original line number Diff line number Diff line
@@ -1066,7 +1066,7 @@ EXPORT_SYMBOL(ath10k_ce_revoke_recv_next);
 * Guts of ath10k_ce_completed_send_next.
 * The caller takes responsibility for any necessary locking.
 */
int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
static int _ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
						 void **per_transfer_contextp)
{
	struct ath10k_ce_ring *src_ring = ce_state->src_ring;
@@ -1118,6 +1118,66 @@ int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,

	return 0;
}

static int _ath10k_ce_completed_send_next_nolock_64(struct ath10k_ce_pipe *ce_state,
						    void **per_transfer_contextp)
{
	struct ath10k_ce_ring *src_ring = ce_state->src_ring;
	u32 ctrl_addr = ce_state->ctrl_addr;
	struct ath10k *ar = ce_state->ar;
	unsigned int nentries_mask = src_ring->nentries_mask;
	unsigned int sw_index = src_ring->sw_index;
	unsigned int read_index;
	struct ce_desc_64 *desc;

	if (src_ring->hw_index == sw_index) {
		/*
		 * The SW completion index has caught up with the cached
		 * version of the HW completion index.
		 * Update the cached HW completion index to see whether
		 * the SW has really caught up to the HW, or if the cached
		 * value of the HW index has become stale.
		 */

		read_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
		if (read_index == 0xffffffff)
			return -ENODEV;

		read_index &= nentries_mask;
		src_ring->hw_index = read_index;
	}

	if (ar->hw_params.rri_on_ddr)
		read_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
	else
		read_index = src_ring->hw_index;

	if (read_index == sw_index)
		return -EIO;

	if (per_transfer_contextp)
		*per_transfer_contextp =
			src_ring->per_transfer_context[sw_index];

	/* sanity */
	src_ring->per_transfer_context[sw_index] = NULL;
	desc = CE_SRC_RING_TO_DESC_64(src_ring->base_addr_owner_space,
				      sw_index);
	desc->nbytes = 0;

	/* Update sw_index */
	sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
	src_ring->sw_index = sw_index;

	return 0;
}

int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
					 void **per_transfer_contextp)
{
	return ce_state->ops->ce_completed_send_next_nolock(ce_state,
							    per_transfer_contextp);
}
EXPORT_SYMBOL(ath10k_ce_completed_send_next_nolock);

static void ath10k_ce_extract_desc_data(struct ath10k *ar,
@@ -1839,6 +1899,7 @@ static const struct ath10k_ce_ops ce_ops = {
	.ce_send_nolock = _ath10k_ce_send_nolock,
	.ce_set_src_ring_base_addr_hi = NULL,
	.ce_set_dest_ring_base_addr_hi = NULL,
	.ce_completed_send_next_nolock = _ath10k_ce_completed_send_next_nolock,
};

static const struct ath10k_ce_ops ce_64_ops = {
@@ -1853,6 +1914,7 @@ static const struct ath10k_ce_ops ce_64_ops = {
	.ce_send_nolock = _ath10k_ce_send_nolock_64,
	.ce_set_src_ring_base_addr_hi = ath10k_ce_set_src_ring_base_addr_hi,
	.ce_set_dest_ring_base_addr_hi = ath10k_ce_set_dest_ring_base_addr_hi,
	.ce_completed_send_next_nolock = _ath10k_ce_completed_send_next_nolock_64,
};

static void ath10k_ce_set_ops(struct ath10k *ar,
+2 −0
Original line number Diff line number Diff line
@@ -329,6 +329,8 @@ struct ath10k_ce_ops {
	void (*ce_set_dest_ring_base_addr_hi)(struct ath10k *ar,
					      u32 ce_ctrl_addr,
					      u64 addr);
	int (*ce_completed_send_next_nolock)(struct ath10k_ce_pipe *ce_state,
					     void **per_transfer_contextp);
};

static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
+21 −8
Original line number Diff line number Diff line
@@ -549,10 +549,10 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.sw_decrypt_mcast_mgmt = true,
		.hw_ops = &wcn3990_ops,
		.decap_align_bytes = 1,
		.num_peers = TARGET_HL_10_TLV_NUM_PEERS,
		.num_peers = TARGET_HL_TLV_NUM_PEERS,
		.n_cipher_suites = 11,
		.ast_skid_limit = TARGET_HL_10_TLV_AST_SKID_LIMIT,
		.num_wds_entries = TARGET_HL_10_TLV_NUM_WDS_ENTRIES,
		.ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT,
		.num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,
		.target_64bit = true,
		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
		.per_ce_irq = true,
@@ -637,11 +637,24 @@ static void ath10k_init_sdio(struct ath10k *ar)
	ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99);
	ath10k_bmi_read32(ar, hi_acs_flags, &param);

	param |= (HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET |
		  HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET |
		  HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE);
	/* Data transfer is not initiated, when reduced Tx completion
	 * is used for SDIO. disable it until fixed
	 */
	param &= ~HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;

	/* Alternate credit size of 1544 as used by SDIO firmware is
	 * not big enough for mac80211 / native wifi frames. disable it
	 */
	param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
	param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
	ath10k_bmi_write32(ar, hi_acs_flags, param);

	/* Explicitly set fwlog prints to zero as target may turn it on
	 * based on scratch registers.
	 */
	ath10k_bmi_read32(ar, hi_option_flag, &param);
	param |= HI_OPTION_DISABLE_DBGLOG;
	ath10k_bmi_write32(ar, hi_option_flag, param);
}

static int ath10k_init_configure_target(struct ath10k *ar)
@@ -2304,8 +2317,8 @@ static int ath10k_core_init_firmware_features(struct ath10k *ar)
		else
			ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
		ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
		ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
			WMI_STAT_PEER;
		ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV |
			WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD;
		ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
		ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC;
		break;
+1 −1
Original line number Diff line number Diff line
@@ -189,7 +189,7 @@ struct ath10k_fw_stats_peer {
	u32 peer_rssi;
	u32 peer_tx_rate;
	u32 peer_rx_rate; /* 10x only */
	u32 rx_duration;
	u64 rx_duration;
};

struct ath10k_fw_extd_stats_peer {
+3 −0
Original line number Diff line number Diff line
@@ -1252,6 +1252,9 @@ static int ath10k_debug_cal_data_fetch(struct ath10k *ar)
	if (WARN_ON(ar->hw_params.cal_data_len > ATH10K_DEBUG_CAL_DATA_LEN))
		return -EINVAL;

	if (ar->hw_params.cal_data_len == 0)
		return -EOPNOTSUPP;

	hi_addr = host_interest_item_address(HI_ITEM(hi_board_data));

	ret = ath10k_hif_diag_read(ar, hi_addr, &addr, sizeof(addr));
Loading