Commit 5016bd24 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2019-02-13' of... 

Merge tag 'drm-intel-fixes-2019-02-13' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

drm/i915 fixes for v5.0-rc7:
- combo phy programming fix
- opregion version check fix for VBT RVDA lookup
- gem mmap ioctl race fix
- fbdev hpd during suspend fix
- array size bounds check fix in pmu

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/877ee3504b.fsf@intel.com
parents d586d571 16eb0f34

drivers/gpu/drm/i915/i915_gem.c

+11 −1
Original line number Diff line number Diff line
@@ -1824,6 +1824,16 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 
	return 0;

}



static inline bool

__vma_matches(struct vm_area_struct *vma, struct file *filp,

	      unsigned long addr, unsigned long size)

{

	if (vma->vm_file != filp)

		return false;



	return vma->vm_start == addr && (vma->vm_end - vma->vm_start) == size;

}



/**

 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address

 *			 it is mapped to.
@@ -1882,7 +1892,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 
			return -EINTR;

		}

		vma = find_vma(mm, addr);

		if (vma)

		if (vma && __vma_matches(vma, obj->base.filp, addr, args->size))

			vma->vm_page_prot =

				pgprot_writecombine(vm_get_page_prot(vma->vm_flags));

		else

drivers/gpu/drm/i915/i915_pmu.c

+15 −7
Original line number Diff line number Diff line
@@ -594,7 +594,8 @@ static void i915_pmu_enable(struct perf_event *event) 
	 * Update the bitmask of enabled events and increment

	 * the event reference counter.

	 */

	GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);

	BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS);

	GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));

	GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0);

	i915->pmu.enable |= BIT_ULL(bit);

	i915->pmu.enable_count[bit]++;
@@ -615,11 +616,16 @@ static void i915_pmu_enable(struct perf_event *event) 
		engine = intel_engine_lookup_user(i915,

						  engine_event_class(event),

						  engine_event_instance(event));

		GEM_BUG_ON(!engine);

		engine->pmu.enable |= BIT(sample);



		GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);

		BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=

			     I915_ENGINE_SAMPLE_COUNT);

		BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=

			     I915_ENGINE_SAMPLE_COUNT);

		GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));

		GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));

		GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);



		engine->pmu.enable |= BIT(sample);

		engine->pmu.enable_count[sample]++;

	}
@@ -649,9 +655,11 @@ static void i915_pmu_disable(struct perf_event *event) 
		engine = intel_engine_lookup_user(i915,

						  engine_event_class(event),

						  engine_event_instance(event));

		GEM_BUG_ON(!engine);

		GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);



		GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));

		GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));

		GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);



		/*

		 * Decrement the reference count and clear the enabled

		 * bitmask when the last listener on an event goes away.
@@ -660,7 +668,7 @@ static void i915_pmu_disable(struct perf_event *event) 
			engine->pmu.enable &= ~BIT(sample);

	}



	GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);

	GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));

	GEM_BUG_ON(i915->pmu.enable_count[bit] == 0);

	/*

	 * Decrement the reference count and clear the enabled

drivers/gpu/drm/i915/i915_pmu.h

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ enum { 
	((1 << I915_PMU_SAMPLE_BITS) + \

	 (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))



#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)



struct i915_pmu_sample {

	u64 cur;

};

drivers/gpu/drm/i915/i915_reg.h

+11 −7
Original line number Diff line number Diff line
@@ -1790,7 +1790,7 @@ enum i915_power_well_id { 
#define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40

#define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40

#define _CNL_PORT_TX_F_LN0_OFFSET		0x162840

#define _CNL_PORT_TX_DW_GRP(port, dw)	(_PICK((port), \

#define _CNL_PORT_TX_DW_GRP(dw, port)	(_PICK((port), \

					       _CNL_PORT_TX_AE_GRP_OFFSET, \

					       _CNL_PORT_TX_B_GRP_OFFSET, \

					       _CNL_PORT_TX_B_GRP_OFFSET, \
@@ -1798,7 +1798,7 @@ enum i915_power_well_id { 
					       _CNL_PORT_TX_AE_GRP_OFFSET, \

					       _CNL_PORT_TX_F_GRP_OFFSET) + \

					       4 * (dw))

#define _CNL_PORT_TX_DW_LN0(port, dw)	(_PICK((port), \

#define _CNL_PORT_TX_DW_LN0(dw, port)	(_PICK((port), \

					       _CNL_PORT_TX_AE_LN0_OFFSET, \

					       _CNL_PORT_TX_B_LN0_OFFSET, \

					       _CNL_PORT_TX_B_LN0_OFFSET, \
@@ -1834,9 +1834,9 @@ enum i915_power_well_id { 


#define _CNL_PORT_TX_DW4_LN0_AE		0x162450

#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0

#define CNL_PORT_TX_DW4_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 4))

#define CNL_PORT_TX_DW4_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 4))

#define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \

#define CNL_PORT_TX_DW4_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))

#define CNL_PORT_TX_DW4_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))

#define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \

					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \

						    _CNL_PORT_TX_DW4_LN0_AE)))

#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(4, port))
@@ -1864,8 +1864,12 @@ enum i915_power_well_id { 
#define   RTERM_SELECT(x)		((x) << 3)

#define   RTERM_SELECT_MASK		(0x7 << 3)



#define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 7))

#define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 7))

#define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))

#define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))

#define ICL_PORT_TX_DW7_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(7, port))

#define ICL_PORT_TX_DW7_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(7, port))

#define ICL_PORT_TX_DW7_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))

#define ICL_PORT_TX_DW7_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))

#define   N_SCALAR(x)			((x) << 24)

#define   N_SCALAR_MASK			(0x7F << 24)

drivers/gpu/drm/i915/intel_ddi.c

+86 −152
Original line number Diff line number Diff line
@@ -494,103 +494,58 @@ static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 
	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */

};



struct icl_combo_phy_ddi_buf_trans {

	u32 dw2_swing_select;

	u32 dw2_swing_scalar;

	u32 dw4_scaling;

};



/* Voltage Swing Programming for VccIO 0.85V for DP */

static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {

				/* Voltage mV  db    */

	{ 0x2, 0x98, 0x0018 },	/* 400         0.0   */

	{ 0x2, 0x98, 0x3015 },	/* 400         3.5   */

	{ 0x2, 0x98, 0x6012 },	/* 400         6.0   */

	{ 0x2, 0x98, 0x900F },	/* 400         9.5   */

	{ 0xB, 0x70, 0x0018 },	/* 600         0.0   */

	{ 0xB, 0x70, 0x3015 },	/* 600         3.5   */

	{ 0xB, 0x70, 0x6012 },	/* 600         6.0   */

	{ 0x5, 0x00, 0x0018 },	/* 800         0.0   */

	{ 0x5, 0x00, 0x3015 },	/* 800         3.5   */

	{ 0x6, 0x98, 0x0018 },	/* 1200        0.0   */

};



/* FIXME - After table is updated in Bspec */

/* Voltage Swing Programming for VccIO 0.85V for eDP */

static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {

				/* Voltage mV  db    */

	{ 0x0, 0x00, 0x00 },	/* 200         0.0   */

	{ 0x0, 0x00, 0x00 },	/* 200         1.5   */

	{ 0x0, 0x00, 0x00 },	/* 200         4.0   */

	{ 0x0, 0x00, 0x00 },	/* 200         6.0   */

	{ 0x0, 0x00, 0x00 },	/* 250         0.0   */

	{ 0x0, 0x00, 0x00 },	/* 250         1.5   */

	{ 0x0, 0x00, 0x00 },	/* 250         4.0   */

	{ 0x0, 0x00, 0x00 },	/* 300         0.0   */

	{ 0x0, 0x00, 0x00 },	/* 300         1.5   */

	{ 0x0, 0x00, 0x00 },	/* 350         0.0   */

};



/* Voltage Swing Programming for VccIO 0.95V for DP */

static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {

				/* Voltage mV  db    */

	{ 0x2, 0x98, 0x0018 },	/* 400         0.0   */

	{ 0x2, 0x98, 0x3015 },	/* 400         3.5   */

	{ 0x2, 0x98, 0x6012 },	/* 400         6.0   */

	{ 0x2, 0x98, 0x900F },	/* 400         9.5   */

	{ 0x4, 0x98, 0x0018 },	/* 600         0.0   */

	{ 0x4, 0x98, 0x3015 },	/* 600         3.5   */

	{ 0x4, 0x98, 0x6012 },	/* 600         6.0   */

	{ 0x5, 0x76, 0x0018 },	/* 800         0.0   */

	{ 0x5, 0x76, 0x3015 },	/* 800         3.5   */

	{ 0x6, 0x98, 0x0018 },	/* 1200        0.0   */

/* icl_combo_phy_ddi_translations */

static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {

						/* NT mV Trans mV db    */

	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */

	{ 0xA, 0x4F, 0x37, 0x00, 0x08 },	/* 350   500      3.1   */

	{ 0xC, 0x71, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */

	{ 0x6, 0x7F, 0x2B, 0x00, 0x14 },	/* 350   900      8.2   */

	{ 0xA, 0x4C, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */

	{ 0xC, 0x73, 0x34, 0x00, 0x0B },	/* 500   700      2.9   */

	{ 0x6, 0x7F, 0x2F, 0x00, 0x10 },	/* 500   900      5.1   */

	{ 0xC, 0x6C, 0x3C, 0x00, 0x03 },	/* 650   700      0.6   */

	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */

};



/* FIXME - After table is updated in Bspec */

/* Voltage Swing Programming for VccIO 0.95V for eDP */

static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {

				/* Voltage mV  db    */

	{ 0x0, 0x00, 0x00 },	/* 200         0.0   */

	{ 0x0, 0x00, 0x00 },	/* 200         1.5   */

	{ 0x0, 0x00, 0x00 },	/* 200         4.0   */

	{ 0x0, 0x00, 0x00 },	/* 200         6.0   */

	{ 0x0, 0x00, 0x00 },	/* 250         0.0   */

	{ 0x0, 0x00, 0x00 },	/* 250         1.5   */

	{ 0x0, 0x00, 0x00 },	/* 250         4.0   */

	{ 0x0, 0x00, 0x00 },	/* 300         0.0   */

	{ 0x0, 0x00, 0x00 },	/* 300         1.5   */

	{ 0x0, 0x00, 0x00 },	/* 350         0.0   */

static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {

						/* NT mV Trans mV db    */

	{ 0x0, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */

	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */

	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */

	{ 0x9, 0x7F, 0x31, 0x00, 0x0E },	/* 200   350      4.9   */

	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */

	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */

	{ 0x9, 0x7F, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */

	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */

	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */

	{ 0x9, 0x7F, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */

};



/* Voltage Swing Programming for VccIO 1.05V for DP */

static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {

				/* Voltage mV  db    */

	{ 0x2, 0x98, 0x0018 },	/* 400         0.0   */

	{ 0x2, 0x98, 0x3015 },	/* 400         3.5   */

	{ 0x2, 0x98, 0x6012 },	/* 400         6.0   */

	{ 0x2, 0x98, 0x900F },	/* 400         9.5   */

	{ 0x4, 0x98, 0x0018 },	/* 600         0.0   */

	{ 0x4, 0x98, 0x3015 },	/* 600         3.5   */

	{ 0x4, 0x98, 0x6012 },	/* 600         6.0   */

	{ 0x5, 0x71, 0x0018 },	/* 800         0.0   */

	{ 0x5, 0x71, 0x3015 },	/* 800         3.5   */

	{ 0x6, 0x98, 0x0018 },	/* 1200        0.0   */

static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {

						/* NT mV Trans mV db    */

	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */

	{ 0xA, 0x4F, 0x37, 0x00, 0x08 },	/* 350   500      3.1   */

	{ 0xC, 0x71, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */

	{ 0x6, 0x7F, 0x2B, 0x00, 0x14 },	/* 350   900      8.2   */

	{ 0xA, 0x4C, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */

	{ 0xC, 0x73, 0x34, 0x00, 0x0B },	/* 500   700      2.9   */

	{ 0x6, 0x7F, 0x2F, 0x00, 0x10 },	/* 500   900      5.1   */

	{ 0xC, 0x6C, 0x3C, 0x00, 0x03 },	/* 650   700      0.6   */

	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */

};



/* FIXME - After table is updated in Bspec */

/* Voltage Swing Programming for VccIO 1.05V for eDP */

static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {

				/* Voltage mV  db    */

	{ 0x0, 0x00, 0x00 },	/* 200         0.0   */

	{ 0x0, 0x00, 0x00 },	/* 200         1.5   */

	{ 0x0, 0x00, 0x00 },	/* 200         4.0   */

	{ 0x0, 0x00, 0x00 },	/* 200         6.0   */

	{ 0x0, 0x00, 0x00 },	/* 250         0.0   */

	{ 0x0, 0x00, 0x00 },	/* 250         1.5   */

	{ 0x0, 0x00, 0x00 },	/* 250         4.0   */

	{ 0x0, 0x00, 0x00 },	/* 300         0.0   */

	{ 0x0, 0x00, 0x00 },	/* 300         1.5   */

	{ 0x0, 0x00, 0x00 },	/* 350         0.0   */

static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {

						/* NT mV Trans mV db    */

	{ 0xA, 0x60, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */

	{ 0xB, 0x73, 0x36, 0x00, 0x09 },	/* 450   650      3.2   */

	{ 0x6, 0x7F, 0x31, 0x00, 0x0E },	/* 450   850      5.5   */

	{ 0xB, 0x73, 0x3F, 0x00, 0x00 },	/* 650   650      0.0   ALS */

	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 650   850      2.3   */

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 850   850      0.0   */

	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */

};



struct icl_mg_phy_ddi_buf_trans {
@@ -871,43 +826,23 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 
	}

}



static const struct icl_combo_phy_ddi_buf_trans *

static const struct cnl_ddi_buf_trans *

icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,

			int type, int *n_entries)

			int type, int rate, int *n_entries)

{

	u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;



	if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {

		switch (voltage) {

		case VOLTAGE_INFO_0_85V:

			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);

			return icl_combo_phy_ddi_translations_edp_0_85V;

		case VOLTAGE_INFO_0_95V:

			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);

			return icl_combo_phy_ddi_translations_edp_0_95V;

		case VOLTAGE_INFO_1_05V:

			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);

			return icl_combo_phy_ddi_translations_edp_1_05V;

		default:

			MISSING_CASE(voltage);

			return NULL;

		}

	} else {

		switch (voltage) {

		case VOLTAGE_INFO_0_85V:

			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);

			return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;

		case VOLTAGE_INFO_0_95V:

			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);

			return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;

		case VOLTAGE_INFO_1_05V:

			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);

			return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;

		default:

			MISSING_CASE(voltage);

			return NULL;

		}

	if (type == INTEL_OUTPUT_HDMI) {

		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);

		return icl_combo_phy_ddi_translations_hdmi;

	} else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {

		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);

		return icl_combo_phy_ddi_translations_edp_hbr3;

	} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {

		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);

		return icl_combo_phy_ddi_translations_edp_hbr2;

	}



	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);

	return icl_combo_phy_ddi_translations_dp_hbr2;

}



static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
@@ -918,8 +853,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por 


	if (IS_ICELAKE(dev_priv)) {

		if (intel_port_is_combophy(dev_priv, port))

			icl_get_combo_buf_trans(dev_priv, port,

						INTEL_OUTPUT_HDMI, &n_entries);

			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,

						0, &n_entries);

		else

			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);

		default_entry = n_entries - 1;
@@ -2275,13 +2210,14 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	enum port port = encoder->port;

	int n_entries;



	if (IS_ICELAKE(dev_priv)) {

		if (intel_port_is_combophy(dev_priv, port))

			icl_get_combo_buf_trans(dev_priv, port, encoder->type,

						&n_entries);

						intel_dp->link_rate, &n_entries);

		else

			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);

	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2462,14 +2398,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 
}



static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,

					 u32 level, enum port port, int type)

					u32 level, enum port port, int type,

					int rate)

{

	const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;

	const struct cnl_ddi_buf_trans *ddi_translations = NULL;

	u32 n_entries, val;

	int ln;



	ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,

						   &n_entries);

						   rate, &n_entries);

	if (!ddi_translations)

		return;
@@ -2478,34 +2415,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 
		level = n_entries - 1;

	}



	/* Set PORT_TX_DW5 Rterm Sel to 110b. */

	/* Set PORT_TX_DW5 */

	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));

	val &= ~RTERM_SELECT_MASK;

	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |

		  TAP2_DISABLE | TAP3_DISABLE);

	val |= SCALING_MODE_SEL(0x2);

	val |= RTERM_SELECT(0x6);

	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);



	/* Program PORT_TX_DW5 */

	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));

	/* Set DisableTap2 and DisableTap3 if MIPI DSI

	 * Clear DisableTap2 and DisableTap3 for all other Ports

	 */

	if (type == INTEL_OUTPUT_DSI) {

		val |= TAP2_DISABLE;

	val |= TAP3_DISABLE;

	} else {

		val &= ~TAP2_DISABLE;

		val &= ~TAP3_DISABLE;

	}

	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);



	/* Program PORT_TX_DW2 */

	val = I915_READ(ICL_PORT_TX_DW2_LN0(port));

	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |

		 RCOMP_SCALAR_MASK);

	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);

	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);

	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);

	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);

	/* Program Rcomp scalar for every table entry */

	val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);

	val |= RCOMP_SCALAR(0x98);

	I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);



	/* Program PORT_TX_DW4 */
@@ -2514,9 +2440,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 
		val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));

		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |

			 CURSOR_COEFF_MASK);

		val |= ddi_translations[level].dw4_scaling;

		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);

		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);

		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);

		I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);

	}



	/* Program PORT_TX_DW7 */

	val = I915_READ(ICL_PORT_TX_DW7_LN0(port));

	val &= ~N_SCALAR_MASK;

	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);

	I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);

}



static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
@@ -2581,7 +2515,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 
	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);



	/* 5. Program swing and de-emphasis */

	icl_ddi_combo_vswing_program(dev_priv, level, port, type);

	icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);



	/* 6. Set training enable to trigger update */

	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));

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