drm/amdgpu: implement gmc_v6_0_emit_flush_gpu_tlb (4fef88bd) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+4 −21

Original line number	Diff line number	Diff line
		@@ -38,6 +38,7 @@
		#include "dce/dce_6_0_sh_mask.h"
		#include "gca/gfx_7_2_enum.h"
		#include "si_enums.h"
		#include "si.h"

		static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
		static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
		@@ -2359,25 +2360,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
		{
		int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

		/* write new base address */
		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) \|
		WRITE_DATA_DST_SEL(0)));
		if (vmid < 8) {
		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid ));
		} else {
		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
		}
		amdgpu_ring_write(ring, 0);
		amdgpu_ring_write(ring, pd_addr >> 12);

		/* bits 0-15 are the VM contexts0-15 */
		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) \|
		WRITE_DATA_DST_SEL(0)));
		amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
		amdgpu_ring_write(ring, 0);
		amdgpu_ring_write(ring, 1 << vmid);
		amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);

		/* wait for the invalidate to complete */
		amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
		@@ -3528,7 +3511,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
		14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
		7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
		17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
		3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
		.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
		.emit_ib = gfx_v6_0_ring_emit_ib,
		@@ -3555,7 +3538,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
		5 + /* gfx_v6_0_ring_emit_hdp_flush */
		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
		7 + /* gfx_v6_0_ring_emit_pipeline_sync */
		17 + /* gfx_v6_0_ring_emit_vm_flush */
		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
		14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
		.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
		.emit_ib = gfx_v6_0_ring_emit_ib,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

+20 −0

Original line number	Diff line number	Diff line
		@@ -362,6 +362,25 @@ static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
		WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
		}

		static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
		unsigned vmid, unsigned pasid,
		uint64_t pd_addr)
		{
		uint32_t reg;

		/* write new base address */
		if (vmid < 8)
		reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
		else
		reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
		amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);

		/* bits 0-15 are the VM contexts0-15 */
		amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);

		return pd_addr;
		}

		static int gmc_v6_0_set_pte_pde(struct amdgpu_device adev, void cpu_pt_addr,
		uint32_t gpu_page_idx, uint64_t addr,
		uint64_t flags)
		@@ -1126,6 +1145,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {

		static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
		.flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
		.emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
		.set_pte_pde = gmc_v6_0_set_pte_pde,
		.set_prt = gmc_v6_0_set_prt,
		.get_vm_pde = gmc_v6_0_get_vm_pde,

drivers/gpu/drm/amd/amdgpu/si.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -24,6 +24,8 @@
		#ifndef __SI_H__
		#define __SI_H__

		#define SI_FLUSH_GPU_TLB_NUM_WREG 2

		void si_srbm_select(struct amdgpu_device *adev,
		u32 me, u32 pipe, u32 queue, u32 vmid);
		int si_set_ip_blocks(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/si_dma.c

+3 −12

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@
		#include <drm/drmP.h>
		#include "amdgpu.h"
		#include "amdgpu_trace.h"
		#include "si.h"
		#include "sid.h"

		const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
		@@ -476,17 +477,7 @@ static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring,
		unsigned vmid, unsigned pasid,
		uint64_t pd_addr)
		{
		amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
		if (vmid < 8)
		amdgpu_ring_write(ring, (0xf << 16) \| (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
		else
		amdgpu_ring_write(ring, (0xf << 16) \| (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
		amdgpu_ring_write(ring, pd_addr >> 12);

		/* bits 0-7 are the VM contexts0-7 */
		amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
		amdgpu_ring_write(ring, (0xf << 16) \| (VM_INVALIDATE_REQUEST));
		amdgpu_ring_write(ring, 1 << vmid);
		amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);

		/* wait for invalidate to complete */
		amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));
		@@ -784,7 +775,7 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
		3 + /* si_dma_ring_emit_hdp_flush */
		3 + /* si_dma_ring_emit_hdp_invalidate */
		6 + /* si_dma_ring_emit_pipeline_sync */
		12 + /* si_dma_ring_emit_vm_flush */
		SI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* si_dma_ring_emit_vm_flush */
		9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */
		.emit_ib_size = 7 + 3, /* si_dma_ring_emit_ib */
		.emit_ib = si_dma_ring_emit_ib,

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