Commit 4fdd2dbc authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlxsw-Various-trap-changes-part-2' 



Ido Schimmel says:

====================
mlxsw: Various trap changes - part 2

This patch set contains another set of small changes in mlxsw trap
configuration. It is the last set before exposing control traps (e.g.,
IGMP query, ARP request) via devlink-trap.

Tested with existing devlink-trap selftests. Please see individual
patches for a detailed changelog.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 4e637c70 10d3757f

drivers/net/ethernet/mellanox/mlxsw/reg.h

+7 −10
Original line number Diff line number Diff line
@@ -5526,8 +5526,6 @@ MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 


enum mlxsw_reg_htgt_trap_group {

	MLXSW_REG_HTGT_TRAP_GROUP_EMAD,

	MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,

	MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
@@ -5542,24 +5540,23 @@ enum mlxsw_reg_htgt_trap_group { 
	MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE,



	__MLXSW_REG_HTGT_TRAP_GROUP_MAX,

	MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1

};



enum mlxsw_reg_htgt_discard_trap_group {

	MLXSW_REG_HTGT_DISCARD_TRAP_GROUP_BASE = MLXSW_REG_HTGT_TRAP_GROUP_MAX,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS,

	MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS,



	__MLXSW_REG_HTGT_TRAP_GROUP_MAX,

	MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1

};



/* reg_htgt_trap_group

drivers/net/ethernet/mellanox/mlxsw/spectrum.c

+24 −16
Original line number Diff line number Diff line
@@ -4052,7 +4052,7 @@ static const struct mlxsw_listener mlxsw_sp_listener[] = { 
	MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, MC_SNOOPING, false),

	MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, NEIGH_DISCOVERY, false),

	MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, NEIGH_DISCOVERY, false),

	MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),

	MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false),

	MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU,

			  MC_SNOOPING, false),

	MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU,
@@ -4066,10 +4066,10 @@ static const struct mlxsw_listener mlxsw_sp_listener[] = { 
	MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),

	MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,

			  false),

	MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),

	MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, IP2ME, false),

	MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),

	MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),

	MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,

	MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, IPV6, false),

	MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, IPV6,

			  false),

	MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),

	MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
@@ -4078,21 +4078,23 @@ static const struct mlxsw_listener mlxsw_sp_listener[] = { 
	MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),

	MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),

	MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),

	MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,

	MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6,

			  false),

	MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISEMENT, TRAP_TO_CPU, IPV6_ND,

	MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISEMENT, TRAP_TO_CPU, IPV6,

			  false),

	MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU,

			  NEIGH_DISCOVERY, false),

	MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISEMENT, TRAP_TO_CPU,

			  NEIGH_DISCOVERY, false),

	MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),

	MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6, false),

	MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,

			  false),

	MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),

	MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),

	MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, IP2ME, false),

	MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, IP2ME, false),

	MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, VRRP, false),

	MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, VRRP, false),

	MLXSW_SP_RXL_MARK(IPV4_BFD, TRAP_TO_CPU, BFD, false),

	MLXSW_SP_RXL_MARK(IPV6_BFD, TRAP_TO_CPU, BFD, false),

	MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD,

			     ROUTER_EXP, false),

	MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD,
@@ -4105,7 +4107,7 @@ static const struct mlxsw_listener mlxsw_sp_listener[] = { 
	MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,

		  false, SP_PKT_SAMPLE, DISCARD),

	/* ACL trap */

	MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),

	MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, FLOW_LOGGING, false),

	/* Multicast Router Traps */

	MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),

	MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
@@ -4165,12 +4167,11 @@ static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 
		case MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:

			rate = 1024;

			burst_size = 7;

			break;

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:

			rate = 1024;

			burst_size = 7;

			break;
@@ -4186,6 +4187,10 @@ static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 
			rate = 360;

			burst_size = 7;

			break;

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD:

			rate = 20 * 1024;

			burst_size = 10;

			break;

		default:

			continue;

		}
@@ -4227,20 +4232,22 @@ static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 
		case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD:

			priority = 5;

			tc = 5;

			break;

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:

			priority = 4;

			tc = 4;

			break;

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:

			priority = 3;

			tc = 3;

			break;

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:

			priority = 2;
@@ -4249,6 +4256,7 @@ static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 
		case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:

		case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:

			priority = 1;

			tc = 1;

			break;

drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c

+4 −2
Original line number Diff line number Diff line
@@ -5003,9 +5003,11 @@ static bool mlxsw_sp_fib6_rt_should_ignore(const struct fib6_info *rt) 
{

	/* Packets with link-local destination IP arriving to the router

	 * are trapped to the CPU, so no need to program specific routes

	 * for them.

	 * for them. Only allow prefix routes (usually one fe80::/64) so

	 * that packets are trapped for the right reason.

	 */

	if (ipv6_addr_type(&rt->fib6_dst.addr) & IPV6_ADDR_LINKLOCAL)

	if ((ipv6_addr_type(&rt->fib6_dst.addr) & IPV6_ADDR_LINKLOCAL) &&

	    (rt->fib6_flags & (RTF_LOCAL | RTF_ANYCAST)))

		return true;



	/* Multicast routes aren't supported, so ignore them. Neighbour

drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c

+11 −6
Original line number Diff line number Diff line
@@ -441,8 +441,6 @@ static const struct mlxsw_sp_trap_item mlxsw_sp_trap_items_arr[] = { 
	},

};



#define MLXSW_SP_THIN_POLICER_ID	(MLXSW_REG_HTGT_TRAP_GROUP_MAX + 1)



static struct mlxsw_sp_trap_policer_item *

mlxsw_sp_trap_policer_item_lookup(struct mlxsw_sp *mlxsw_sp, u32 id)

{
@@ -487,14 +485,21 @@ mlxsw_sp_trap_item_lookup(struct mlxsw_sp *mlxsw_sp, u16 id) 


static int mlxsw_sp_trap_cpu_policers_set(struct mlxsw_sp *mlxsw_sp)

{

	struct mlxsw_sp_trap *trap = mlxsw_sp->trap;

	char qpcr_pl[MLXSW_REG_QPCR_LEN];

	u16 hw_id;



	/* The purpose of "thin" policer is to drop as many packets

	 * as possible. The dummy group is using it.

	 */

	__set_bit(MLXSW_SP_THIN_POLICER_ID, mlxsw_sp->trap->policers_usage);

	mlxsw_reg_qpcr_pack(qpcr_pl, MLXSW_SP_THIN_POLICER_ID,

			    MLXSW_REG_QPCR_IR_UNITS_M, false, 1, 4);

	hw_id = find_first_zero_bit(trap->policers_usage, trap->max_policers);

	if (WARN_ON(hw_id == trap->max_policers))

		return -ENOBUFS;



	__set_bit(hw_id, trap->policers_usage);

	trap->thin_policer_hw_id = hw_id;

	mlxsw_reg_qpcr_pack(qpcr_pl, hw_id, MLXSW_REG_QPCR_IR_UNITS_M,

			    false, 1, 4);

	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpcr), qpcr_pl);

}
@@ -503,7 +508,7 @@ static int mlxsw_sp_trap_dummy_group_init(struct mlxsw_sp *mlxsw_sp) 
	char htgt_pl[MLXSW_REG_HTGT_LEN];



	mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY,

			    MLXSW_SP_THIN_POLICER_ID, 0, 1);

			    mlxsw_sp->trap->thin_policer_hw_id, 0, 1);

	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);

}

drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.h

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ struct mlxsw_sp_trap { 
	struct mlxsw_sp_trap_item *trap_items_arr;

	u64 traps_count; /* Number of registered traps */



	u16 thin_policer_hw_id;



	u64 max_policers;

	unsigned long policers_usage[]; /* Usage bitmap */

};

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